公开(公告)号：US09111750B2

公开(公告)日：2015-08-18

申请号：US13931363

申请日：2013-06-28

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Rui Zhou

IPC: H01L21/8232 ,  H01L29/267 ,  H01L27/02 ,  H01L21/82 ,  H01L21/8252 ,  H01L27/06

CPC classification number: H01L27/0248 ,  H01L21/8213 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0617 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract translation: 提出了一种单片集成半导体组件。 半导体组件包括包含碳化硅（SiC）的衬底，并且在衬底上制造氮化镓（GaN）半导体器件。 半导体组件还包括在衬底中或衬底上制造的至少一个瞬态电压抑制器（TVS）结构，其中TVS结构与GaN半导体器件电接触。 当跨越GaN半导体器件的施加电压大于阈值电压时，TVS结构被配置为以穿通模式，雪崩模式或其组合工作。 还提出了制造单片集成半导体组件的方法。

公开(公告)号：US20150162743A1

公开(公告)日：2015-06-11

申请号：US14102632

申请日：2013-12-11

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Mark Gerard Roberto ,  David Mulford Shaddock ,  Joe Walter Kirstein

IPC: H02H9/04

CPC classification number: H01L27/0248 ,  H02H9/041 ,  Y10T29/49117

Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

Abstract translation: 提供了一种制造过电压保护装置和过电压电路保护装置的方法。 过电压电路保护装置包括并联耦合的多个瞬态电压抑制（TVS）装置。

公开(公告)号：US08987858B2

公开(公告)日：2015-03-24

申请号：US13846380

申请日：2013-03-18

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Stephen Daley Arthur

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/861

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/265 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/8618 ,  H01L2924/10272

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract translation: 提供瞬态电压抑制（TVS）装置和形成装置的方法。 该器件包括由第一导电类型材料形成的第一层宽带隙半导体材料，在第一层的至少一部分上由第二导电类型材料形成的第二层宽带隙半导体材料，并且包括离子注入 材料结构在0.1微米（μm）和22.0μm厚之间，第二层使用穿透物理学操作，以及在第二层的至少一部分上由第一导电类型材料形成的第三层宽带隙半导体材料。

公开(公告)号：US20150028469A1

公开(公告)日：2015-01-29

申请号：US13950736

申请日：2013-07-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Rui Zhou ,  Peter Almern Losee

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L27/0248 ,  H01L2924/0002

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract translation: 提出了一种单片集成半导体组件。 半导体组件包括包括硅（Si）的衬底，并且在衬底上制造氮化镓（GaN）半导体器件。 半导体组件还包括在衬底中或衬底上制造的至少一个瞬态电压抑制器（TVS）结构，其中TVS结构与GaN半导体器件电接触。 当跨越GaN半导体器件的施加电压大于阈值电压时，TVS结构被配置为以穿通模式，雪崩模式或其组合工作。 还提出了制造单片集成半导体组件的方法。