公开(公告)号：US20150348913A1

公开(公告)日：2015-12-03

申请号：US14818039

申请日：2015-08-04

Applicant: Globalfoundries Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L23/544 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

公开(公告)号：US09177873B2

公开(公告)日：2015-11-03

申请号：US13953532

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alok Vaid ,  Carsten Hartig ,  Lokesh Subramany

IPC: G06F17/00 ,  H01L21/66 ,  G03F7/20

CPC classification number: H01L22/00 ,  G03F7/70616 ,  H01L22/12

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.

Abstract translation: 提供了用于制造和测量半导体器件结构的物理特征的方法和系统。 制造半导体器件结构的示例性方法包括从计量工具获得用于半导体材料的晶片的原始测量数据，并且至少部分地基于原始测量数据和设计值来调整由测量工具使用的测量模型 参数。 晶片具有该设计参数的值以及其上制造的半导体器件结构的属性，其中测量模型由测量工具用于将原始测量数据转换为该属性的测量值。

公开(公告)号：US20150033201A1

公开(公告)日：2015-01-29

申请号：US13953532

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alok Vaid ,  Carsten Hartig ,  Lokesh Subramany

IPC: G06F17/50

CPC classification number: H01L22/00 ,  G03F7/70616 ,  H01L22/12

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.

Abstract translation: 提供了用于制造和测量半导体器件结构的物理特征的方法和系统。 制造半导体器件结构的示例性方法包括从计量工具获得用于半导体材料的晶片的原始测量数据，并且至少部分地基于原始测量数据和设计值来调整由测量工具使用的测量模型 参数。 晶片具有该设计参数的值以及其上制造的半导体器件结构的属性，其中测量模型由测量工具用于将原始测量数据转换为该属性的测量值。

公开(公告)号：US20140201693A1

公开(公告)日：2014-07-17

申请号：US13741645

申请日：2013-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Nedal Saleh ,  Alok Vaid

IPC: G06F17/50

CPC classification number: H01L22/12 ,  G03F7/70625 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.

Abstract translation: 各种实施例包括用于生成用于散射分析的集成电路（IC）库的计算机实现的方法，计算机程序产品和系统。 在某些情况下，方法包括：获得关于至少一个IC芯片的芯片设计数据; 获得关于所述至少一个IC芯片的用户输入数据; 并且使用其原始格式的芯片设计数据和其原始格式的用户输入数据运行IC库定义程序，IC库定义程序的运行包括：基于所述至少一个IC芯片确定所述至少一个IC芯片的处理变化 芯片设计数据和用户输入数据; 将过程变化转换为形状变化数据; 并将文本格式的形状变化数据提供给用于散射分析的散点建模程序。