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    METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING
    21.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING 有权

    公开(公告)号：US20210027005A1

    公开(公告)日：2021-01-28

    申请号：US17070708

    申请日：2020-10-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Lei Yuan ,  Juhan Kim

    IPC: G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  G06F30/394

    Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.

    STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION
    22.
    发明申请
    STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION 审中-公开

    公开(公告)号：US20190333853A1

    公开(公告)日：2019-10-31

    申请号：US16411237

    申请日：2019-05-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

    IPC: H01L23/528 ,  H01L23/50 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

    Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library
    23.
    发明授权
    Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library 有权

    公开(公告)号：US10360334B2

    公开(公告)日：2019-07-23

    申请号：US15428449

    申请日：2017-02-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

    IPC: G06F17/50

    Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

    Antenna diode circuit for manufacturing of semiconductor devices
    25.
    发明授权
    Antenna diode circuit for manufacturing of semiconductor devices 有权

    公开(公告)号：US10096595B2

    公开(公告)日：2018-10-09

    申请号：US15286196

    申请日：2016-10-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain ,  Anurag Mittal ,  Sangmoon Kim

    IPC: H01L27/02 ,  H01L27/06 ,  G06F17/50 ,  H01L27/11 ,  H01L29/66

    Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

    CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY
    26.
    发明申请
    CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO STRAIN RELAXATION IN STANDARD CELL LIBRARY 审中-公开

    公开(公告)号：US20180225406A1

    公开(公告)日：2018-08-09

    申请号：US15428449

    申请日：2017-02-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Navneet Jain ,  Mahbub Rashed ,  Juhan Kim

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

    Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

    CMOS-based integrated circuit products with isolated P-wells for body-biasing transistor devices
    28.
    发明授权
    CMOS-based integrated circuit products with isolated P-wells for body-biasing transistor devices 有权

    公开(公告)号：US10777558B1

    公开(公告)日：2020-09-15

    申请号：US16352420

    申请日：2019-03-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juhan Kim

    IPC: H01L29/06 ,  H01L27/092

    Abstract: One illustrative integrated circuit product disclosed herein comprises a PFET region and an NFET region defined in an active semiconductor layer of an SOI substrate, a deep N-well region positioned in the base semiconductor substrate, first and second isolated P-wells positioned in the base semiconductor substrate below the PFET region and the NFET region, respectively, wherein the first and second isolated P-wells engage the deep N-well region, and a deep isolation structure that extends into the deep N-well region, wherein a first portion of the deep isolation structure is laterally positioned between the first isolated P-well and the second isolated P-well to electrically isolate, in a horizontal direction, the first isolated P-well from the second isolated P-well. The product also includes at least one PFET transistor and at least one NFET transistor.

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