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    Special construct for continuous non-uniform active region FinFET standard cells
    1.
    发明授权
    Special construct for continuous non-uniform active region FinFET standard cells 有权

    公开(公告)号：US10199378B2

    公开(公告)日：2019-02-05

    申请号：US15857202

    申请日：2017-12-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

    Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

    METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS WITH TRIPLE PATTERNED METAL LAYER STRUCTURES
    4.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS WITH TRIPLE PATTERNED METAL LAYER STRUCTURES 审中-公开

    公开(公告)号：US20170316140A1

    公开(公告)日：2017-11-02

    申请号：US15140183

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Juhan Kim ,  Mahbub Rashed

    IPC: G06F17/50 ,  H01L27/02 ,  H01L23/535

    CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

    Abstract: At least one method, apparatus and system disclosed herein for forming a semiconductor device comprising a plurality of cells having metal features formed using triple patterning processes. An overall pattern layout is created for a first cell that is to be manufactured using a triple patterning process for forming a plurality of metal features on a metal layer. A first color metal feature is formed in the metal layer. The first color metal feature is associated with a first patterning process of the triple patterning process. A second color metal feature is formed in the metal layer. The second color metal feature is associated with a second patterning process of the triple patterning process. A third color metal feature is formed in the metal layer. The third color metal feature is associated with a third patterning process of the triple patterning process. At least one of the first, second, and third color metal features is re-colorable.

    DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME
    5.
    发明申请
    DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME 有权
    用于集成电路产品的密封包装标准电池及其制造方法

    公开(公告)号：US20140339647A1

    公开(公告)日：2014-11-20

    申请号：US13893524

    申请日：2013-05-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Suresh Venkatesan

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/8238

    CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

    Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构

    CMOS-BASED INTEGRATED CIRCUIT PRODUCTS WITH ISOLATED P-WELLS FOR BODY-BIASING TRANSISTOR DEVICES
    6.
    发明申请
    CMOS-BASED INTEGRATED CIRCUIT PRODUCTS WITH ISOLATED P-WELLS FOR BODY-BIASING TRANSISTOR DEVICES 审中-公开

    公开(公告)号：US20200295004A1

    公开(公告)日：2020-09-17

    申请号：US16352420

    申请日：2019-03-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Juhan Kim

    IPC: H01L27/092 ,  H01L29/06

    Abstract: One illustrative integrated circuit product disclosed herein comprises a PFET region and an NFET region defined in an active semiconductor layer of an SOI substrate, a deep N-well region positioned in the base semiconductor substrate, first and second isolated P-wells positioned in the base semiconductor substrate below the PFET region and the NFET region, respectively, wherein the first and second isolated P-wells engage the deep N-well region, and a deep isolation structure that extends into the deep N-well region, wherein a first portion of the deep isolation structure is laterally positioned between the first isolated P-well and the second isolated P-well to electrically isolate, in a horizontal direction, the first isolated P-well from the second isolated P-well. The product also includes at least one PFET transistor and at least one NFET transistor.

    Structure and method for flexible power staple insertion
    7.
    发明授权
    Structure and method for flexible power staple insertion 有权

    公开(公告)号：US10658294B2

    公开(公告)日：2020-05-19

    申请号：US16411237

    申请日：2019-05-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L23/50 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118

    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

    POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE
    8.
    发明申请
    POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE 审中-公开

    公开(公告)号：US20200117226A1

    公开(公告)日：2020-04-16

    申请号：US16159831

    申请日：2018-10-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Arif A. Siddiqi ,  Juhan Kim ,  Mahbub Rashed

    IPC: G05F3/20 ,  G11C5/14

    Abstract: Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal.

    Structure and method for flexible power staple insertion
    9.
    发明授权
    Structure and method for flexible power staple insertion 有权

    公开(公告)号：US10366954B1

    公开(公告)日：2019-07-30

    申请号：US15962065

    申请日：2018-04-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

    IPC: H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02 ,  H01L23/50

    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

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