公开(公告)号：US09214567B2

公开(公告)日：2015-12-15

申请号：US14020096

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/44 ,  H01L29/786 ,  H01L23/62 ,  H01L27/02

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract translation: 在半导体衬底的一个区域中设置电熔丝。 电子熔断器包括从底部到顶部的基底金属半导体合金部分，第一金属半导体合金部分，第二金属半导体部分，第三金属半导体合金部分和第四金属半导体合金部分的垂直堆叠，其中 第一金属半导体合金部分和第三金属半导体部分具有垂直偏移并且不延伸超过第二金属半导体合金部分和第四金属半导体合金部分的垂直边缘的外边缘。

公开(公告)号：US10199220B2

公开(公告)日：2019-02-05

申请号：US15652413

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09793113B2

公开(公告)日：2017-10-17

申请号：US15075668

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Dominic J. Schepis ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi

IPC: H01L21/20 ,  H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/0243 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31 ,  H01L21/311 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66446 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.

公开(公告)号：US09331201B2

公开(公告)日：2016-05-03

申请号：US13906428

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other.

Abstract translation: 提供半导体结构，其半导体鳍片具有可变的高度，而没有任何不适当的形貌。 半导体结构包括具有第一半导体表面和第二半导体表面的半导体衬底，其中第一半导体表面垂直偏移并位于第二半导体表面上方。 氧化物区域直接位于第一半导体表面和/或第二半导体表面上。 具有第一高度的第一组第一半导体散热片位于半导体衬底的第一半导体表面之上。 具有第二高度的第二组第二半导体翅片位于第二半导体表面上方，其中第二高度不同于第一高度，并且其中每个第一半导体鳍片和每个第二半导体鳍片具有彼此共面的最顶面。

公开(公告)号：US20160086886A1

公开(公告)日：2016-03-24

申请号：US14957842

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L23/525 ,  H01L23/62 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.