公开(公告)号：US20190019798A1

公开(公告)日：2019-01-17

申请号：US16133176

申请日：2018-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66818

Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.

公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

公开(公告)号：US20170271032A1

公开(公告)日：2017-09-21

申请号：US15615660

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C29/52 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C7/04 ,  G11C11/412 ,  G11C11/419

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

公开(公告)号：US09202552B2

公开(公告)日：2015-12-01

申请号：US14105939

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Randy W. Mann ,  Sangmoon J. Kim

IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/412 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract translation: 提供了具有提高存取晶体管物理放置对称性的双端口静态随机存取存储器（SRAM）位单元结构。 比特单元结构可以包括例如两对并行下拉晶体管。 比特单元结构还可以包括形成第一端口的通过栅极晶体管PGLA和PGRA，以及形成第二端口的通过栅极晶体管PGLB和PGRB。 通路栅极晶体管PGLA和PGLB可以彼此相邻，并且位单元结构的第一侧，以及栅极晶体管PGRA和PGRB可以彼此相邻，并且位单元结构的第二侧。 每个通栅晶体管PGLA和PGLB可以与一对并联下拉晶体管中的一个的下拉晶体管中的一个连接。 类似地，每个通栅晶体管PGRA和PGRB可以与另一对并联下拉晶体管的下拉晶体管中的一个连接。