公开(公告)号：US10811409B2

公开(公告)日：2020-10-20

申请号：US16161620

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Guowei Xu ,  Jian Gao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

公开(公告)号：US10797049B2

公开(公告)日：2020-10-06

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US10784143B2

公开(公告)日：2020-09-22

申请号：US16263650

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang ,  Yue Zhong

IPC: H01L29/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/3213 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

公开(公告)号：US20200227404A1

公开(公告)日：2020-07-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/522

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

公开(公告)号：US20190259619A1

公开(公告)日：2019-08-22

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

公开(公告)号：US10153209B1

公开(公告)日：2018-12-11

申请号：US15888408

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L27/02 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US10734233B2

公开(公告)日：2020-08-04

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US10600876B2

公开(公告)日：2020-03-24

申请号：US15974037

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Rongtao Lu

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.

公开(公告)号：US10522538B1

公开(公告)日：2019-12-31

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.