公开(公告)号：US10804199B2

公开(公告)日：2020-10-13

申请号：US16140545

申请日：2018-09-25

申请人： GLOBALFOUNDRIES INC.

发明人： Yongjun Shi ,  Ruilong Xie ,  Nan Fu ,  Chun Yu Wong

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522 ,  H01L21/321 ,  H01L21/3105

摘要： A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

公开(公告)号：US10910276B1

公开(公告)日：2021-02-02

申请号：US16589789

申请日：2019-10-01

申请人： GLOBALFOUNDRIES INC.

发明人： Yongjun Shi ,  Xinyuan Dou ,  Chun Yu Wong ,  Hongliang Shen ,  Baofu Zhu

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78

摘要： A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.

公开(公告)号：US20190148492A1

公开(公告)日：2019-05-16

申请号：US15811990

申请日：2017-11-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC分类号： H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02

CPC分类号： H01L29/0847 ,  H01L21/02576 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

摘要： A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US20190131433A1

公开(公告)日：2019-05-02

申请号：US15795879

申请日：2017-10-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

摘要： Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20200043779A1

公开(公告)日：2020-02-06

申请号：US16052085

申请日：2018-08-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC分类号： H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/28

摘要： Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

申请人： GLOBALFOUNDRIES INC.

发明人： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

摘要： Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

申请人： GLOBALFOUNDRIES INC.

发明人： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238

摘要： Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC分类号： H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

摘要： Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10164010B1

公开(公告)日：2018-12-25

申请号：US15798546

申请日：2017-10-31

申请人： GLOBALFOUNDRIES INC.

发明人： Wei Hong ,  Hsien-Ching Lo ,  Haiting Wang ,  Yanping Shen ,  Yi Qi ,  Yongjun Shi ,  Hui Zang ,  Edward Reis

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L27/088

摘要： Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.

公开(公告)号：US10546775B1

公开(公告)日：2020-01-28

申请号：US16052085

申请日：2018-08-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC分类号： H01L21/70 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

摘要： Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.