公开(公告)号：US11579360B2

公开(公告)日：2023-02-14

申请号：US17354408

申请日：2021-06-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Qizhi Liu

IPC: G02B6/12 ,  G02B6/34 ,  G02B6/124

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a vertically oriented semiconductor waveguide with a first end on a semiconductor layer. The vertically oriented semiconductor waveguide includes a first sidewall and a second sidewall opposite the first sidewall. A reflective material is along the second sidewall of the vertically oriented semiconductor waveguide. A first plurality of grating protrusions extends from the first sidewall of the vertically oriented semiconductor waveguide.

公开(公告)号：US11488950B2

公开(公告)日：2022-11-01

申请号：US17173611

申请日：2021-02-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Vibhor Jain ,  Anthony K. Stamper ,  Qizhi Liu ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/732 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73

Abstract: Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

公开(公告)号：US11362201B1

公开(公告)日：2022-06-14

申请号：US17120916

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sarah McTaggart ,  Qizhi Liu ,  Vibhor Jain ,  Mark Levy ,  Paula Fisher ,  James R. Elliott

IPC: H01L29/737 ,  H01L29/66

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

公开(公告)号：US11177347B2

公开(公告)日：2021-11-16

申请号：US16830783

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

公开(公告)号：US11127831B2

公开(公告)日：2021-09-21

申请号：US16788914

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.

公开(公告)号：US11063139B2

公开(公告)日：2021-07-13

申请号：US16748055

申请日：2020-01-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Judson Holt

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

公开(公告)号：US20210091236A1

公开(公告)日：2021-03-25

申请号：US16790084

申请日：2020-02-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08

Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.