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    COMPILER FOR TRANSLATING BETWEEN A VIRTUAL IMAGE PROCESSOR INSTRUCTION SET ARCHITECTURE (ISA) AND TARGET HARDWARE HAVING A TWO-DIMENSIONAL SHIFT ARRAY STRUCTURE
    22.
    发明申请
    COMPILER FOR TRANSLATING BETWEEN A VIRTUAL IMAGE PROCESSOR INSTRUCTION SET ARCHITECTURE (ISA) AND TARGET HARDWARE HAVING A TWO-DIMENSIONAL SHIFT ARRAY STRUCTURE 有权
    用于虚拟图像处理器指令集架构（ISA）和具有两维位移结构的目标硬件之间的转换的编译器

    公开(公告)号：US20160313984A1

    公开(公告)日：2016-10-27

    申请号：US14694856

    申请日：2015-04-23

    Applicant: Google Inc.

    Inventor： Albert Meixner

    IPC: G06F9/45 ,  G06F9/30

    CPC classification number: G06F8/451 ,  G06F8/441 ,  G06F8/4441 ,  G06F8/445 ,  G06F9/30003 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

    Abstract: A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

    Abstract translation: 描述了一种方法，其包括将包括更高级程序代码的更高级程序代码转换为具有指令格式的指令格式，该指令格式从具有第一和第二坐标的存储器将要访问的像素从正交坐标系转换为针对具有阵列的硬件架构的较低级指令 的执行通道和能够沿两个不同轴移动数据的移位寄存器阵列结构。 转换包括用具有移位寄存器阵列结构内的数据的较低电平移位指令代替具有指令格式的较高电平指令。

    CONVOLUTIONAL NEURAL NETWORK ON PROGRAMMABLE TWO DIMENSIONAL IMAGE PROCESSOR
    25.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK ON PROGRAMMABLE TWO DIMENSIONAL IMAGE PROCESSOR 审中-公开

    公开(公告)号：US20180005075A1

    公开(公告)日：2018-01-04

    申请号：US15631906

    申请日：2017-06-23

    Applicant: Google Inc.

    Inventor： Ofer Shacham ,  David Patterson ,  William R. Mark ,  Albert Meixner ,  Daniel Frederic Finchelstein ,  Jason Rupert Redgrave

    IPC: G06K9/56 ,  G06T5/20 ,  G06K9/46

    Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.

    Statistics Operations On Two Dimensional Image Processor
    26.
    发明申请
    Statistics Operations On Two Dimensional Image Processor 审中-公开

    公开(公告)号：US20180005061A1

    公开(公告)日：2018-01-04

    申请号：US15596286

    申请日：2017-05-16

    Applicant: Google Inc.

    Inventor： Edward Chang ,  Daniel Frederic Finchelstein ,  Szepo Robert Hung ,  Albert Meixner ,  Ofer Shacham

    IPC: G06K9/00 ,  G11C19/00

    CPC classification number: G06K9/00986 ,  G06T1/20 ,  G11C19/00

    Abstract: A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.

    Virtual linebuffers for image signal processors
    28.
    发明授权
    Virtual linebuffers for image signal processors 有权

    公开(公告)号：US09749548B2

    公开(公告)日：2017-08-29

    申请号：US14603354

    申请日：2015-01-22

    Applicant: GOOGLE INC.

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60

    CPC classification number: H04N5/262 ,  G06T1/20 ,  G06T1/60

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR
    29.
    发明申请
    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR 审中-公开

    公开(公告)号：US20170242695A1

    公开(公告)日：2017-08-24

    申请号：US15591955

    申请日：2017-05-10

    Applicant: Google Inc.

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

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