公开(公告)号：US20110167243A1

公开(公告)日：2011-07-07

申请号：US12652641

申请日：2010-01-05

申请人： Sherman H. Yip ,  Paul Caprioli

发明人： Sherman H. Yip ,  Paul Caprioli

IPC分类号： G06F9/38 ,  G06F9/312 ,  G06F12/08

CPC分类号： G06F9/3842 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3895

摘要： Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.

摘要翻译： 公开了技术和结构，用于支持检查点的处理器以有效的侦察模式进行操作，同时最大数量的支持的检查点是活动的。 在侦察模式下的操作可以包括使用旁路逻辑和一组寄存器存储位置来存储和/或转发在侦察模式期间计算的飞行中指令结果。 这些转发结果可以在侦察模式期间用于计算其他飞行中指令的存储器加载地址，并且处理器可以相应地使数据从这些计算的存储器加载地址中预取。 该组寄存器存储位置可以包括工作寄存器文件或多端口寄存器文件的活动部分。

公开(公告)号：US07716457B2

公开(公告)日：2010-05-11

申请号：US11654271

申请日：2007-01-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

IPC分类号： G06F9/00

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F11/3612

摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.

摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。

公开(公告)号：US07634639B2

公开(公告)日：2009-12-15

申请号：US11210557

申请日：2005-08-23

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip ,  Guarav Garg ,  Ketaki Rao

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip ,  Guarav Garg ,  Ketaki Rao

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3863 ,  G06F9/3885

摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.

摘要翻译： 本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。 系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。 在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。 如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。 在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。 系统接下来取消状态指示。 然后，系统在正常执行模式下继续发出以程序顺序执行的指令。 以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。

公开(公告)号：US07617421B2

公开(公告)日：2009-11-10

申请号：US11495452

申请日：2006-07-27

申请人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

发明人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

IPC分类号： G06F11/00

CPC分类号： G06F11/1407 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/467 ,  G06F11/0724 ,  G06F11/079

摘要： One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.

摘要翻译： 本发明的一个实施例提供一种在事务执行期间报告故障原因的系统。 在操作期间，系统在程序中事务地执行指令块。 如果指令块的事务执行成功完成，则系统将在事务执行期间进行更改，并通过指令块恢复程序的正常非事务性执行。 否则，如果指令块的事务执行失败，则系统将丢弃在事务执行期间所做的更改，并记录指示事务执行失败的原因的故障信息。

公开(公告)号：US20090204761A1

公开(公告)日：2009-08-13

申请号：US12029889

申请日：2008-02-12

申请人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

发明人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

IPC分类号： G06F12/00

CPC分类号： G06F12/125 ,  G06F12/0864 ,  Y02D10/13

摘要： Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.

摘要翻译： 本发明的实施例提供了一种在偏斜相关高速缓存中以最近最近使用的方式替换条目的系统。 系统从接收缓存行地址开始。 然后系统使用高速缓存行地址生成两个或多个索引。 接下来，系统使用两个或更多个索引生成两个或更多个中间索引。 然后，系统使用两个或更多个索引中的至少一个或两个或更多个中间索引来在一个或多个查找表中执行查找，其中查找返回标识最近最近使用的方式的值。 接下来，系统以最近最少使用的方式替换条目。

公开(公告)号：US20080172548A1

公开(公告)日：2008-07-17

申请号：US11654270

申请日：2007-01-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.

摘要翻译： 本发明的一个实施例提供了一种用于在推测执行期间测量处理器性能的系统。 系统通过在正常执行模式下执行指令来启动。 然后，系统进入推测执行情节，其中指令被推测地执行而不致力于处理器的架构状态。 在进入推测执行情节时，系统启用推测执行监视器。 然后，系统使用推测执行监视器在推测执行情节期间监视指令，以记录与推测执行情节相关的数据值。 返回到正常执行模式后，系统将禁用推测执行监视器。 由推测执行监视器记录的数据值有助于在推测执行期间测量处理器的性能。

公开(公告)号：US20080126883A1

公开(公告)日：2008-05-29

申请号：US11495452

申请日：2006-07-27

申请人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

发明人： Paul Caprioli ,  Sherman H. Yip ,  Shailender Chaudhry

IPC分类号： G06F11/14

CPC分类号： G06F11/1407 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/467 ,  G06F11/0724 ,  G06F11/079

摘要： One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.

摘要翻译： 本发明的一个实施例提供一种在事务执行期间报告故障原因的系统。 在操作期间，系统在程序中事务地执行指令块。 如果指令块的事务执行成功完成，则系统将在事务执行期间进行更改，并通过指令块恢复程序的正常非事务性执行。 否则，如果指令块的事务执行失败，则系统将丢弃在事务执行期间所做的更改，并记录指示事务执行失败的原因的故障信息。

公开(公告)号：US07293163B2

公开(公告)日：2007-11-06

申请号：US10807093

申请日：2004-03-22

申请人： Paul Caprioli ,  Sherman H. Yip

发明人： Paul Caprioli ,  Sherman H. Yip

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other hand, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.

摘要翻译： 本发明的一个实施例提供了一种动态地调整执行前处理器的侵略性的系统。 如果在程序执行期间遇到与数据有关的失速条件，则系统进入执行模式，其中由于未解决的数据相关性而无法执行的指令被延迟，并且其他非延迟指令以程序顺序执行。 如果在执行提前模式期间遇到非数据相关的失速条件，则系统进入侦察模式，其中，推测性地执行指令以预取将来的负载，但是结果并未提交到执行前处理器的架构状态。 另一方面，如果在执行提前模式下解决了未解决的数据依赖关系，则输入延迟模式并执行延迟指令。 在该延迟模式期间，如果再次延迟某些指令，则系统确定是否在执行模式下继续执行。 如果它确定这样做，系统将以执行方式恢复执行，否则以非侵略模式恢复执行。

公开(公告)号：US20110264862A1

公开(公告)日：2011-10-27

申请号：US12768641

申请日：2010-04-27

申请人： Martin Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

发明人： Martin Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0855

摘要： Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.

摘要翻译： 公开了关于减少在实现侦察的处理器中重新启动管道的延迟的技术。 在一个实施例中，处理器可以使用配置为彼此并行地获取和重新获取指令的两个指令获取单元来减少流水线重新启动等待时间。 在一些实施例中，响应于确定将针对一个或多个延迟指令尝试提交操作，处理器可以通过启动重新获取指令来减少流水线重新启动等待时间。 在其他实施例中，处理器可以通过响应于接收到对高速缓存已经接收到对一组数据的请求的指示，通过发起重新获取指令来减少流水线重新启动等待时间，其中在由缓存发送指示之前， 数据存在于缓存中。

公开(公告)号：US09086889B2

公开(公告)日：2015-07-21

申请号：US12768641

申请日：2010-04-27

申请人： Martin Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

发明人： Martin Karlsson ,  Sherman H. Yip ,  Shailender Chaudhry

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0855

摘要： Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.

摘要翻译： 公开了关于减少在实现侦察的处理器中重新启动管道的延迟的技术。 在一个实施例中，处理器可以使用配置为彼此并行地获取和重新获取指令的两个指令获取单元来减少流水线重新启动等待时间。 在一些实施例中，响应于确定将针对一个或多个延迟指令尝试提交操作，处理器可以通过启动重新获取指令来减少流水线重新启动等待时间。 在其他实施例中，处理器可以通过响应于接收到对高速缓存已经接收到对一组数据的请求的指示，通过发起重新获取指令来减少流水线重新启动等待时间，其中在由缓存发送指示之前， 数据存在于缓存中。