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公开(公告)号：US20110264862A1
公开(公告)日：2011-10-27
申请号：US12768641
申请日：2010-04-27
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F12/0855
摘要： Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.
摘要翻译： 公开了关于减少在实现侦察的处理器中重新启动管道的延迟的技术。 在一个实施例中，处理器可以使用配置为彼此并行地获取和重新获取指令的两个指令获取单元来减少流水线重新启动等待时间。 在一些实施例中，响应于确定将针对一个或多个延迟指令尝试提交操作，处理器可以通过启动重新获取指令来减少流水线重新启动等待时间。 在其他实施例中，处理器可以通过响应于接收到对高速缓存已经接收到对一组数据的请求的指示，通过发起重新获取指令来减少流水线重新启动等待时间，其中在由缓存发送指示之前， 数据存在于缓存中。
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公开(公告)号：US09086889B2
公开(公告)日：2015-07-21
申请号：US12768641
申请日：2010-04-27
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F12/0855
摘要： Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.
摘要翻译： 公开了关于减少在实现侦察的处理器中重新启动管道的延迟的技术。 在一个实施例中，处理器可以使用配置为彼此并行地获取和重新获取指令的两个指令获取单元来减少流水线重新启动等待时间。 在一些实施例中，响应于确定将针对一个或多个延迟指令尝试提交操作，处理器可以通过启动重新获取指令来减少流水线重新启动等待时间。 在其他实施例中，处理器可以通过响应于接收到对高速缓存已经接收到对一组数据的请求的指示，通过发起重新获取指令来减少流水线重新启动等待时间，其中在由缓存发送指示之前， 数据存在于缓存中。
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公开(公告)号：US20110179254A1
公开(公告)日：2011-07-21
申请号：US12688633
申请日：2010-01-15
CPC分类号： G06F9/30079 , G06F9/3802 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching instructions. In some embodiments, the processor stalls the instruction fetch unit until a condition that originally caused the processor to operate in the speculative-execution mode is resolved. In alternative embodiments, the processor maintains the stall of the instruction fetch unit until the pipe-clearing event has been completed (i.e., has been handled in the processor).
摘要翻译： 所描述的实施例涉及推测性地执行指令的处理器。 在操作期间，处理器经常以推测执行模式执行指令。 当在推测执行模式下执行指令时检测到即将发生的管道清除事件，处理器停止指令提取单元以防止指令获取单元获取指令。 在一些实施例中，处理器停止指令提取单元，直到最初导致处理器以推测执行模式操作的条件被解决为止。 在替代实施例中，处理器维持指令提取单元的停止，直到管道清除事件已经完成（即，已经在处理器中处理）。
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4.发明授权公开(公告)号：US07757068B2
公开(公告)日：2010-07-13
申请号：US11654270
申请日：2007-01-16
IPC分类号： G06F7/38
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3863 , G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F11/348 , G06F2201/88 , G06F2201/885
摘要： One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.
摘要翻译： 本发明的一个实施例提供了一种用于在推测执行期间测量处理器性能的系统。 系统通过在正常执行模式下执行指令来启动。 然后，系统进入推测执行情节，其中指令被推测地执行而不被提交到处理器的架构状态。 在进入推测执行情节时，系统启用推测执行监视器。 然后，系统使用推测执行监视器在推测执行情节期间监视指令，以记录与推测执行情节相关的数据值。 返回到正常执行模式后，系统将禁用推测执行监视器。 由推测执行监视器记录的数据值有助于在推测执行期间测量处理器的性能。
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5.发明授权Mechanism for hardware tracking of return address after tail call elimination of return-type instruction 有权尾部呼叫消除返回类型指令后返回地址的硬件跟踪机制公开(公告)号：US07610474B2
公开(公告)日：2009-10-27
申请号：US11352147
申请日：2006-02-10
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
摘要翻译： 检测到返回类型指令的尾部消除消息后，技术维护返回地址堆栈（RAS）内容和RAS顶层（TOS）指针的对齐。 在本发明的至少一个实施例中，一种装置包括处理器流水线和至少第一返回地址堆栈，用于在处理器流水线的第一级保持与指令流相关联的返回地址堆栈。 响应于检测到与第一级遇到的第一呼叫类型指令相关联的一个或多个指令的尾部呼叫消除序列，处理器流水线被配置为维持第一返回地址堆栈不变。 否则处理器流水线被配置为将与第一调用类型指令相关联的返回地址推送到第一返回地址堆栈。
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6.发明授权Circuitry and method for accessing an associative cache with parallel determination of data and data availability 有权用于通过并行确定数据和数据可用性访问关联高速缓存的电路和方法公开(公告)号：US07461208B1
公开(公告)日：2008-12-02
申请号：US11155147
申请日：2005-06-16
IPC分类号： G06F13/16
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6082
摘要： A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.
摘要翻译： 提供了一种用于访问关联高速缓存的电路。 电路包括与关联高速缓存通信的数据选择电路和结果并行处理电路。 结果并行处理电路被配置为确定来自关联高速缓存的数据的访问是否是高速缓存命中，高速缓存未命中或高速缓存错误预测中的一个。 电路还包括与数据选择电路和结果并行处理电路通信的存储器。 存储器被配置为存储存储体选择表，由此存储体选择表被配置为包括定义从其输出数据的关联高速缓存的多个存储区之一的选择的条目。 还描述了访问关联高速缓存的方法。
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公开(公告)号：US08364900B2
公开(公告)日：2013-01-29
申请号：US12029889
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/125 , G06F12/0864 , Y02D10/13
摘要： Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.
摘要翻译： 本发明的实施例提供了一种在偏斜相关高速缓存中以最近最近使用的方式替换条目的系统。 系统从接收缓存行地址开始。 然后系统使用高速缓存行地址生成两个或多个索引。 接下来，系统使用两个或更多个索引生成两个或更多个中间索引。 然后，系统使用两个或更多个索引中的至少一个或两个或更多个中间索引来在一个或多个查找表中执行查找，其中查找返回标识最近最近使用的方式的值。 接下来，系统以最近最少使用的方式替换条目。
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公开(公告)号：US20110179258A1
公开(公告)日：2011-07-21
申请号：US12688679
申请日：2010-01-15
CPC分类号： G06F12/0859 , G06F9/30189 , G06F9/383 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.
摘要翻译： 所描述的实施例提供了一种用于在处理器中执行指令的系统。 在所描述的实施例中，当在执行执行模式中执行指令时检测到用于延迟指令的输入数据的返回，处理器确定在错误缓冲器中对于返回的输入数据的相应条目中是否设置了重放位。 如果重放位被设置，则处理器转换到延迟执行模式以执行延迟指令。 否则，处理器继续执行执行模式的指令。
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9.发明授权Method and apparatus for sampling instructions on a processor that supports speculative execution 有权用于在支持推测性执行的处理器上对指令进行采样的方法和装置公开(公告)号：US07418581B2
公开(公告)日：2008-08-26
申请号：US11405965
申请日：2006-04-17
IPC分类号： G06F9/30
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.
摘要翻译： 本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。 系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。 然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此可以使用所记录的信息来确定处理器的性能。
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公开(公告)号：US08984264B2
公开(公告)日：2015-03-17
申请号：US12688679
申请日：2010-01-15
CPC分类号： G06F12/0859 , G06F9/30189 , G06F9/383 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.
摘要翻译： 所描述的实施例提供了一种用于在处理器中执行指令的系统。 在所描述的实施例中，当在执行执行模式中执行指令时检测到用于延迟指令的输入数据的返回，处理器确定在错误缓冲器中对于返回的输入数据的相应条目中是否设置了重放位。 如果重放位被设置，则处理器转换到延迟执行模式以执行延迟指令。 否则，处理器继续执行执行模式的指令。
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