公开(公告)号：US07420789B2

公开(公告)日：2008-09-02

申请号：US11256228

申请日：2005-10-21

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： The invention discloses an integrated circuit that includes a first device in a first power domain; a second device in a second power domain; and an electrostatic discharge (ESD) bus coupled to the first and second devices for providing a current path to dissipate an ESD current during an ESD event occurring at the first or second device. The ESD bus is disposed across the first and second power domains without having a diode module interposed therebetween, thereby preventing the ESD current from flowing through the first and second devices.

摘要翻译： 本发明公开了一种集成电路，其包括第一功率域中的第一器件; 第二功率域中的第二设备; 以及耦合到第一和第二器件的静电放电（ESD）总线，用于在第一或第二器件发生的ESD事件期间提供电流路径以耗散ESD电流。 ESD总线跨越第一和第二功率域设置，而不插入二极管模块，从而防止ESD电流流过第一和第二器件。

公开(公告)号：US07274544B2

公开(公告)日：2007-09-25

申请号：US10971271

申请日：2004-10-21

申请人： Ker-Min Chen ,  Cheng-Ming Chiang

发明人： Ker-Min Chen ,  Cheng-Ming Chiang

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： The present disclosure is directed toward electrostatic device protection for semiconductor devices. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit may comprise a first circuit coupled to a voltage bus and to the gate of a first transisto, the first circuit comprising a metal-oxide semiconductor (MOS) transistor; and a second circuit coupled to the voltage bus, to ground, and to the gate of the transistor of the first circuit. The MOS transistor of the first circuit may be a PMOS transistor whose source is coupled to the voltage bus, whose drain is coupled to the gate of the first transistor, whose gate is coupled to the second circuit, and whose well is coupled to a floating N-well.

摘要翻译： 本公开涉及用于半导体器件的静电装置保护。 用于为半导体电路提供静电放电（ESD）保护的电路可以包括耦合到电压总线的第一电路和第一转换器的栅极，第一电路包括金属氧化物半导体（MOS）晶体管; 以及第二电路，其耦合到所述电压总线，接地并且连接到所述第一电路的晶体管的栅极。 第一电路的MOS晶体管可以是PMOS晶体管，其源极耦合到电压总线，其漏极耦合到第一晶体管的栅极，其栅极耦合到第二电路，并且其阱耦合到浮置 N井

公开(公告)号：US20070091523A1

公开(公告)日：2007-04-26

申请号：US11256287

申请日：2005-10-21

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： The present invention discloses an IC implemented with ESD protection system. In one embodiment, the includes a first device in a first power domain, and a second device in a second power domain. A buffer module is coupled between the first device and the second device for allowing a signal to pass across between the first and second devices during a normal operation, and for increasing an impedance between the first and second devices during an electrostatic discharge (ESD) event, thereby reducing a possibility of having an ESD current flow from the first device to the second device.

摘要翻译： 本发明公开了一种采用ESD保护系统实现的IC。 在一个实施例中，包括第一功率域中的第一设备和第二功率域中的第二设备。 缓冲模块耦合在第一设备和第二设备之间，用于允许信号在正常操作期间在第一和第二设备之间通过，并且用于在静电放电（ESD）事件期间增加第一和第二设备之间的阻抗 从而减少ESD电流从第一器件流向第二器件的可能性。

公开(公告)号：US20060049847A1

公开(公告)日：2006-03-09

申请号：US10937153

申请日：2004-09-07

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H03K19/0175

CPC分类号： H03K19/00315

摘要： An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer. The input/output buffer further comprises an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad, a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode, and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver.

公开(公告)号：US08492795B1

公开(公告)日：2013-07-23

申请号：US13433006

申请日：2012-03-28

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L27/10 ,  G03C1/00

CPC分类号： H01L27/0207 ,  H01L27/11898

摘要： An integrated circuit (IC) including a core area containing active devices and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. The at least one I/O cell includes a gate orientation, a pre-driver module, and at least one post-driver module. The pre-driver module and the at least one post-driver module are offset from each other by an angle between zero and ninety degrees with respect to the gate orientation. The gate orientation for every one of the at least one I/O cell is substantially the same.

摘要翻译： 一种集成电路（IC），包括包含有源器件的核心区域和被配置为将信号传入和移出核心区域的至少一个输入/输出（I / O）单元。 所述至少一个I / O单元包括门取向，预驱动器模块和至少一个后驱动器模块。 预驱动器模块和至少一个后驱动器模块相对于门方位彼此偏移了零到九十度之间的角度。 所述至少一个I / O单元中的每一个的栅极取向基本相同。

公开(公告)号：US20100013109A1

公开(公告)日：2010-01-21

申请号：US12176602

申请日：2008-07-21

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099

摘要： This invention discloses an integrated circuit (IC) chip which comprises a first, second and third bonding pad connected exclusively to a first, second and third probing pad, respectively, wherein the first bonding pad, the second probing pad and the third bonding pad are substantially aligned linearly with the second probing pad being placed between the first and third bonding pad.

摘要翻译： 本发明公开了一种集成电路（IC）芯片，其包括分别专门连接到第一，第二和第三探针焊盘的第一，第二和第三焊盘，其中第一焊盘，第二探测焊盘和第三焊盘是 基本上与第二探测垫直线对准地放置在第一和第三焊盘之间。

公开(公告)号：US07594198B2

公开(公告)日：2009-09-22

申请号：US11711949

申请日：2007-02-27

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： G06F17/50

CPC分类号： H03K17/0814 ,  H01L27/0251 ,  H03K17/08142 ,  H03K17/16 ,  H03K17/161 ,  H03K17/6872

摘要： A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the same against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell.

摘要翻译： 微芯片包括围绕至少一个核心电路区域的至少一个I / O区域。 所述I / O区还包括具有连接到第一I / O焊盘的至少一个第一后驱动器器件的第一I / O单元; 具有连接到第二I / O焊盘的至少一个第二后驱动器器件的第二I / O单元; 和由第一I / O单元和第二I / O单元共享的静电放电（ESD）簇，用于在ESD事件期间保护ESD静电放电ESD保护ESD电流，从而减小第一I / O单元的总宽度，而第二I / I / O单元。

公开(公告)号：US20080111193A1

公开(公告)日：2008-05-15

申请号：US11595120

申请日：2006-11-10

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L23/5228 ,  H01L27/0266 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

摘要翻译： 本发明公开了一种用于静电放电（ESD）器件的镇流电阻器，其包括形成ESD放电晶体管的源极/漏极的至少一个第一有源区，至少一个具有蛇形形状的电阻元件形成在半导体的单层中 结构，其中所述电阻元件具有耦合到所述第一有源区的第一端子和耦合到包括电源（Vdd或Vss）焊盘的焊盘的第二端子。

公开(公告)号：US07330702B2

公开(公告)日：2008-02-12

申请号：US11045050

申请日：2005-01-31

申请人： Ker-Min Chen ,  Tsung-Yang Hung

发明人： Ker-Min Chen ,  Tsung-Yang Hung

IPC分类号： H04B1/40

CPC分类号： H04B1/38

摘要： In one embodiment, the disclosure relates to a method and apparatus for inter-chip wireless communication system. The system includes a first microprocessor having a plurality of non-contact ports and a first RF communication circuit integrated with the first microprocessor; a second microprocessor also having a plurality of non-contact ports and a second RF communication circuit integrated therein. An RF communication protocol can be configured to receive data from each of the non-contact ports in parallel, multiplex and translate the data to a serial RF signal. Data communication can be accomplished using the wireless communication circuit on each chip. The RF communication between the first and the second integrated circuits using the communication protocol defines a non capacitive-coupling of the first and the second die.

摘要翻译： 在一个实施例中，本发明涉及一种用于芯片间无线通信系统的方法和装置。 该系统包括具有多个非接触端口的第一微处理器和与第一微处理器集成的第一RF通信电路; 第二微处理器还具有集成在其中的多个非接触端口和第二RF通信电路。 RF通信协议可以被配置为并行地从每个非接触端口接收数据，将数据复用并转换为串行RF信号。 可以使用每个芯片上的无线通信电路来实现数据通信。 使用通信协议的第一和第二集成电路之间的RF通信定义了第一和第二管芯的非电容耦合。

公开(公告)号：US07221183B2

公开(公告)日：2007-05-22

申请号：US11064362

申请日：2005-02-23

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H03K17/16

CPC分类号： H03K3/356182 ,  H01L27/0251

摘要： A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A diode, a NMOS device, and a PMOS device are used as regenerative devices in three examples. These three examples exhibit improved electrostatic discharge (ESD) tolerance.

摘要翻译： 具有一个高输出和一个低电平输出的系列的低电平电路包括一个再生装置，与高端和低端输出端耦合，至少一个PMOS器件和一个NMOS 器件分别与高电压和低电压耦合。 在三个示例中，二极管，NMOS器件和PMOS器件用作再生器件。 这三个示例表现出改善的静电放电（ESD）容限。