公开(公告)号：US20220379602A1

公开(公告)日：2022-12-01

申请号：US17884329

申请日：2022-08-09

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG ,  James Michael GARDNER

IPC: B41J2/045

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20220349872A1

公开(公告)日：2022-11-03

申请号：US17865253

申请日：2022-07-14

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： John Rossi ,  Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

IPC: G01N33/49 ,  A61K47/18 ,  A61K47/26 ,  G01N27/327 ,  G01N33/66

Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

公开(公告)号：US20220080738A9

公开(公告)日：2022-03-17

申请号：US16768626

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Quinton B. WEAVER ,  James Michael GARDNER ,  David N. OLSEN ,  Anthony D. STUDER

IPC: B41J2/175

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit to receive, via the interface, requests corresponding to different sensor IDs with the component connected to the apparatus. The logic circuit is to transmit, via the interface, a digital value in response to each request. The digital values corresponding to the different sensor IDs are distinct.

公开(公告)号：US20210334391A1

公开(公告)日：2021-10-28

申请号：US16495227

申请日：2018-12-03

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Stephen D. PANSHIN ,  Jefferson P. WARD ,  David Owen ROETHIG

IPC: G06F21/60 ,  G06F13/42 ,  G06F21/44 ,  B41J2/175

Abstract: In an example, a method comprises, by logic circuitry associated with a replaceable print apparatus component, responding to a first validation request sent via an I2C bus to a first address associated with the logic circuitry with a first validation response; and responding to a second validation request sent via the I2C bus to a second address associated with the logic circuitry with a second validation response.

公开(公告)号：US20210316550A1

公开(公告)日：2021-10-14

申请号：US16768588

申请日：2019-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Boon Bing NG

IPC: B41J2/045 ,  G11C7/10 ,  G06F13/16

Abstract: A memory circuit for a print component including plurality of I/O pads, including a first analog pad and a second analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component, including an analog signal path connected to the first analog pad and the second analog pad, the first analog pad electrically isolated from the second analog pad to interrupt the analog signal path to the print component. The memory circuit further includes a memory component to store memory values associated with the print component, and a control circuit to, in response to a sequence of operating signals received by the I/O pads representing a memory read, provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20210229426A1

公开(公告)日：2021-07-29

申请号：US16957517

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first memory cells, a plurality of first storage elements, and control logic. Each first memory cell stores a customization bit. Each first storage element is coupled to a corresponding first memory cell. The control logic, in response to a reset signal, reads the customization bit stored in each first memory cell and latches each customization bit in a corresponding first storage element.

公开(公告)号：US20210221120A1

公开(公告)日：2021-07-22

申请号：US16768023

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: An integrated circuit for a fluidic die including an address bus to communicate a set of addresses, a first group of die configuration functions including a first address driver to drive a first portion of an address of the set of addresses on the address bus, a second group of die configuration functions including a second address driver to drive a second portion of the address of the set of addresses on the address bus, and an array of fluid actuating devices addressable by the set of addresses communicated via the address bus.

公开(公告)号：US20210213750A1

公开(公告)日：2021-07-15

申请号：US16768626

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Quinton B. WEAVER ,  James Michael GARDNER ,  David N. OLSEN ,  Anthony D. STUDER

IPC: B41J2/175

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit to receive, via the interface, requests corresponding to different sensor IDs with the component connected to the apparatus. The logic circuit is to transmit, via the interface, a digital value in response to each request. The digital values corresponding to the different sensor IDs are distinct.

公开(公告)号：US20210213746A1

公开(公告)日：2021-07-15

申请号：US16767582

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Sirena LU ,  Scott A. LINN

IPC: B41J2/175 ,  G06F13/42 ,  B41J2/045

Abstract: A logic circuitry package for a replaceable print apparatus component includes a first at least one analog cell of a first type, a second at least one analog cell of a second type, an analog-digital converter (ADC), an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, requests to perform measurements to selected ones of the at least one first and second analog cells. The at least one logic circuit is configured to selectively route analog signals from the selected analog cells to the ADC based on the requests.

公开(公告)号：US20210162738A1

公开(公告)日：2021-06-03

申请号：US16959065

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.