Abstract:
A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2n−1-bit first temperature code by using high n bits of an input 2n-bit binary digital signal, generate a 2n−1-bit second temperature code by using low n bits of the 2n-bit binary digital signal, and control, by using the 2n−1-bit first temperature code and the 2n−1-bit second temperature code, a working sequence of 2n×2n−1 unit switches.
Abstract:
A wireless communication method and apparatus, and a radio frequency subsystem are provided. The apparatus includes a local oscillator circuit, configured to provide a local oscillator signal; a radio frequency transmitter coupled to the local oscillator circuit, configured to send a first signal on a first carrier based on the local oscillator signal provided by the local oscillator circuit; a radio frequency receiver coupled to the local oscillator circuit, configured to receive a second signal on a second carrier based on a local oscillator signal of a same frequency as the local oscillator signal provided by the local oscillator circuit; and a digital frequency converter coupled to the radio frequency transmitter and the radio frequency receiver, configured to provide a digital frequency conversion operation to compensate for a frequency difference between a center frequency of the first carrier and a center frequency of the second carrier.
Abstract:
A communication device includes a first radio frequency circuit; a plurality of second radio frequency circuits; and a power division/combination network, including a signal combining port and a plurality of signal dividing ports, where the signal combining port is coupled to the first radio frequency circuit, and the plurality of signal dividing ports is coupled to the plurality of second radio frequency circuits. The power division/combination network includes a power divider/combiner. Two ends of a first signal transmission network in the power divider/combiner are coupled to a common port and a first dividing port respectively, two ends of a second signal transmission network are coupled to the common port and a second dividing port respectively, and a mode tuning circuit is coupled to the first signal transmission network.
Abstract:
This application relates to the field of communication technologies, and discloses a communication method and apparatus. The method includes: The terminal device generates capability information, where the capability information includes an overall frequency separation class of the terminal device, and the overall frequency separation class indicates a maximum frequency separation between a lowest component carrier and a highest component carrier included in an uplink component carrier and a downlink component carrier supported by the terminal device; and the terminal device sends the capability information to the network device.
Abstract:
This application discloses a radio frequency receiver and a wireless communication apparatus. The radio frequency receiving apparatus includes: a first receiver, including a first receive channel and a second receive channel; a second receiver, including a third receive channel, where both maximum signal bandwidths supported by the first receive channel and the second receive channel are less than a maximum signal bandwidth supported by the third receive channel; an analog-to-digital converter ADC group, including a plurality of ADCs, where the plurality of ADCs includes a first ADC and a second ADC; and a channel router, configured to allocate an ADC.
Abstract:
A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.
Abstract:
A method for controlling a digital fractional frequency-division phase-locked loop and a phase-locked loop are disclosed. The phase-locked loop includes a control apparatus, a TDC, a DLF, a DCO, a DIV, and an SDM. The control apparatus performs delay processing on an active edge of a reference clock according to a frequency control word and a frequency division control word to obtain a delayed reference clock; and sends the delayed reference clock to the TDC so that the TDC performs phase discrimination processing on the delayed reference clock and a feedback clock. A control apparatus added to a phase-locked loop may perform delay processing on a reference clock according to a current frequency control word and a current frequency division control word, so that a feedback clock and a delayed reference clock have active edges that approximately correspond in time.