公开(公告)号：US20190196716A1

公开(公告)日：2019-06-27

申请号：US16284609

申请日：2019-02-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Florian Longnos ,  Wei Yang

IPC: G06F3/06 ,  G06F12/06

Abstract: A memory access technology and a computer system, where the computer system includes a memory controller, a media controller, and a non-volatile memory (NVM) coupled to the media controller. After receiving a first read command from the memory controller, the media controller may read first data from the NVM based on a first address in the first read command. Then the media controller transmit, to the memory controller, at least two fixed-length data subblocks and metadata of the at least two data subblocks in response to at least two first send commands received from the memory controller. The metadata includes a location identifier indicating an offset of a corresponding data subblock in the first data. Thus, the memory controller obtains the first data based on the at least two data subblocks and location identifiers in the metadata.

公开(公告)号：US10127955B2

公开(公告)日：2018-11-13

申请号：US15607360

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Wei Yang ,  Junfeng Zhao

IPC: G11C8/10 ,  G11C8/16 ,  G06F3/06

Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.

公开(公告)号：US20180053569A1

公开(公告)日：2018-02-22

申请号：US15802781

申请日：2017-11-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Yongbing Huang ,  Rui He

IPC: G11C29/00 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G11C29/783 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091

Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

公开(公告)号：US20240095531A1

公开(公告)日：2024-03-21

申请号：US18521763

申请日：2023-11-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei Jiang ,  Shihai Xiao

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A method trains a neural network model in a computer system. The neural network model includes one or more layers each including one or more neurons. The one or more layers include at least one first layer and one last layer. Each neurons are configured to perform forward propagation of one or more input values by applying weights to the one or more input values and generating an output value based on a function applied to the sum of the weighted input values. The neurons of any given layer, but the last layer, of the one or more layers are connected with the one or more neurons of a consecutive layer. The neurons of any given layer, but the first layer, of the one or more layers are connected with the one or more neurons of a preceding layer.

公开(公告)号：US11784756B2

公开(公告)日：2023-10-10

申请号：US16893748

申请日：2020-06-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Florian Longnos ,  Feng Yang

IPC: H04L1/1607 ,  G06F3/06

CPC classification number: H04L1/1642 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory access technology and a computer system, where the computer system includes a memory controller and a medium controller connected to the memory controller. In the computer system, when detecting that an error occurs in first data that is returned by the medium controller in response to a first send command, the memory controller determines sequence information of the first send command in a plurality of send commands that have been sent by the memory controller within a time period from a time point at which the first send command is sent to a current time, and sends a data retransmission command to the medium controller to instruct the medium controller to resend the first data based on the sequence information.

公开(公告)号：US20230152977A1

公开(公告)日：2023-05-18

申请号：US18154532

申请日：2023-01-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Chuanzeng Liang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory management technology may be applied to a computer system including a dynamic random-access (DRAM). According to the memory management technology, a corresponding row management policy may be executed based on an access type of memory access, where the access type of the memory access includes a read access or a write access.

公开(公告)号：US20220206686A1

公开(公告)日：2022-06-30

申请号：US17569911

申请日：2022-01-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Florian Longnos ,  Wei Yang

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16

Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.

公开(公告)号：US10997078B2

公开(公告)日：2021-05-04

申请号：US16455466

申请日：2019-06-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Lei Fang ,  Florian Longnos

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0831 ,  G06F12/1045

Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.

公开(公告)号：US10586608B2

公开(公告)日：2020-03-10

申请号：US15802781

申请日：2017-11-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Yongbing Huang ,  Rui He

IPC: G11C11/40 ,  G11C29/00 ,  G11C11/406 ,  G11C11/4091

Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

公开(公告)号：US10346701B2

公开(公告)日：2019-07-09

申请号：US15695681

申请日：2017-09-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

IPC: G06K9/00 ,  G06K9/62

Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.