Abstract:
Embodiments of the present invention provide a method and apparatus for determining a connection relationship between an antenna feeding port of a base station and an antenna port. The method includes: receiving, via one antenna port, a signal sent by a base station, and acquiring the signal via a Smart Bias-Tee in an antenna and a port of a remote control unit in the antenna, where the antenna port, the Smart Bias-Tee, and the port of the remote control unit are in a one-to-one correspondence; determining, according to the Smart Bias-Tee and the port of the remote control unit that acquire the signal, the antenna port that receives the signal; and sending, to the base station, identification information of the antenna port that receives the signal, and/or identification information of an antenna corresponding to the antenna port. Then accuracy and convenience in determining the connection relationship can be improved.
Abstract:
A multi-band multi-path receiving and transmitting device and method are provided. The multi-band multi-path receiving and transmitting device includes at least two multi-frequency couplers, a multi-band transceiver, and a signal processing module. The multi-band transceiver includes at least two first frequency band receiving branches and at least two second frequency band receiving branches, and the multi-band transceiver is adopted to decrease the number of the transceivers, thereby reducing the material cost and the mounting cost of the base station system.
Abstract:
A multi-band multi-path receiving and transmitting device and method, and a base station system are provided. The multi-band multi-path receiving and transmitting device includes a broadband antenna, at least two multi-frequency couplers, a multi-band transceiver, and a signal processing module. The multi-band transceiver is adopted to decrease the number of the transceivers, thereby reducing the material cost and the mounting cost of the base station system.
Abstract:
The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.
Abstract:
The invention discloses a packaging structure, including a substrate, a fan-out unit, and a wiring layer. The fan-out unit includes a first chip and a second chip. The first chip includes a first pin array, and the second chip includes a second pin array. The fan-out unit further includes a third pin array. The first pin array, the second pin array, and the third pin array are all disposed facing the substrate. The wiring layer bridges over between the first pin array and the second pin array, and is configured to connect each first pin in the first pin array to a corresponding second pin in the second pin array. The substrate is provided with a soldering pad that is electrically connected to a wiring layer in the substrate, and the third pin array is connected to the soldering pad.
Abstract:
A packaged chip, including a package structure, a redistribution structure, and a carrier, where the package structure includes a first chip and a second chip adjacent to the first chip. The redistribution structure is configured to electrically connect the first chip and the carrier, and is configured to electrically connect the second chip and the carrier. The redistribution structure includes a main body made of an insulating material and a bump solder array welded to a lower surface of the main body. A metal redistribution wire group and a metal interconnection wire group that has a curve or bend design are disposed in the main body. An upper surface of the main body of the redistribution structure adheres to a lower surface of the first chip and a lower surface of the second chip. The redistribution structure is welded to an upper surface of the carrier.