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21.发明授权Method and circuit for increased noise immunity for clocking signals in high speed digital systems 失效用于提高高速数字系统中时钟信号抗噪声的方法和电路公开(公告)号：US07034566B2
公开(公告)日：2006-04-25
申请号：US10777952
申请日：2004-02-12
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
摘要翻译： 描述了用于在高速数字系统中提高时钟信号的抗噪声性的方面。 这些方面包括使用用于多个负载电路的单个缓冲电路来缓冲差分时钟信号，并且配置单个缓冲器电路以适应接收差分时钟信号的负载电路的数量的变化。 配置在调整到负载电路数量的变化时，可实现时钟信号输出的恒定带宽和电压电平。
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公开(公告)号：US08183920B2
公开(公告)日：2012-05-22
申请号：US12828238
申请日：2010-06-30
IPC分类号： H03F3/45
CPC分类号： H03G3/004 , H03F1/0205 , H03F3/189 , H03F3/45632 , H03F2200/294 , H03F2200/555 , H03F2203/45418
摘要： A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.
摘要翻译： 可变增益放大器包括被配置为接收一对差分信号的第一差分信号的第一共模（CM）节点。 第一调节器耦合到第一CM节点，第一调节器被配置为生成第一CM偏移。 第二CM节点被配置为接收该对差分信号的第二差分信号。 第二调节器耦合到第二CM节点，第二调节器被配置为生成第二CM偏移。 在一个实施例中，第一CM偏移和第二CM偏移量一起包括净CM偏移，净CM偏移被配置为替换当前源净偏移。
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23.发明授权System and circuit for determining data signal jitter via asynchronous sampling 有权用于通过异步采样确定数据信号抖动的系统和电路公开(公告)号：US07930120B2
公开(公告)日：2011-04-19
申请号：US12103689
申请日：2008-04-15
CPC分类号： G01R31/31725 , G01R29/26 , G01R31/31709 , H04L1/205
摘要： A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译： 用于通过异步采样确定数据信号抖动的系统和电路提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。
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24.发明授权Critical path redundant logic for mitigation of hardware across chip variation 有权用于缓解跨芯片变化的硬件的关键路径冗余逻辑公开(公告)号：US07898286B2
公开(公告)日：2011-03-01
申请号：US12369066
申请日：2009-02-11
申请人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
摘要翻译： 用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。 逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和 绕过每个通过的功能路径。
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25.发明授权High speed serial link output stage having self adaptation for various impairments 失效具有各种损伤的自适应的高速串行链路输出级公开(公告)号：US07769057B2
公开(公告)日：2010-08-03
申请号：US12175846
申请日：2008-07-18
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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公开(公告)号：US20090004978A1
公开(公告)日：2009-01-01
申请号：US11769128
申请日：2007-06-27
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.
摘要翻译： 提供了一种用于操作集成在微电子元件中的发射器的方法。 在校准阶段中，存储多个操作参数，用于在多个对应的操作条件中的每一个下控制发射机的频率响应。 在检测到诸如温度或电源电压电平的操作条件时，将相应的存储的操作参数应用于发射机以控制频率响应。
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28.发明授权Method and apparatus for constructing a synchronous signal diagram from asynchronously sampled data 失效用于从异步采样数据构造同步信号图的方法和装置公开(公告)号：US07383160B1
公开(公告)日：2008-06-03
申请号：US11427860
申请日：2006-06-30
IPC分类号： G06F19/00
CPC分类号： H04L1/205 , G01R31/31709
摘要： A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
摘要翻译： 一种用于提供信号图的低成本和生产可集成技术的方法。 数据信号被边缘检测和异步采样（或者时钟信号被锁存）。 将数据信号或第二信号与可设置的阈值电压进行比较并采样。 边缘和比较数据根据扫描时基折叠以找到最小抖动周期。 信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。 对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。 该技术在可设置的阈值电压范围内重复。 然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。
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29.发明授权Flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权灵活的多模逻辑元件用于可配置的混合逻辑信号分配路径公开(公告)号：US07362138B1
公开(公告)日：2008-04-22
申请号：US11613516
申请日：2006-12-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K19/0016 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译： 公开了一种被配置为以多种操作模式之一操作的多模电路。 特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。 多模电路的工作模式可以动态地选择。 一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。
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30.发明申请Method and Apparatus for Determining Data Signal Jitter Via Asynchronous Sampling 失效用于通过异步采样确定数据信号抖动的方法和装置公开(公告)号：US20080004821A1
公开(公告)日：2008-01-03
申请号：US11427940
申请日：2006-06-30
IPC分类号： G06F19/00
CPC分类号： G01R31/31725 , G01R29/26 , G01R31/31709 , H04L1/205
摘要： A method and apparatus for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译： 用于通过异步采样来确定数据信号抖动的方法和装置提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。
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