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1.发明授权High speed serial link output stage having self adaptation for various impairments 失效具有各种损伤的自适应的高速串行链路输出级公开(公告)号：US07769057B2
公开(公告)日：2010-08-03
申请号：US12175846
申请日：2008-07-18
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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公开(公告)号：US07698802B2
公开(公告)日：2010-04-20
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.
摘要翻译： 一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。
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公开(公告)号：US07411422B2
公开(公告)日：2008-08-12
申请号：US11103789
申请日：2005-04-12
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/03885 , H04L25/0272 , H04L25/03343
摘要： A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.
摘要翻译： 高速串行数据通信系统包括用于校正均衡误差的规定，特别是由均衡器非理想性引入的错误。 在数据发射机上实现均衡，并且基于差分对的输出处的动态电流减法。 当位时间> 0时，误差电流从总驱动器电流中去除或减去，从而保持从位时间0到位时间> 0的恒定总电流。 通过使用相反性别的场效应晶体管减去位时间> 0时的电流，也可以实现相同的结果。 误差电流可以从仿真或使用驱动程序的副本通过反馈凭经验确定。 用于实现均衡纠错的电路和所得到的电网分析被显示和描述。
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4.发明授权Method for performing high speed serial link output stage having self adaptation for various impairments 失效用于执行具有针对各种损伤的自适应的高速串行链路输出级的方法公开(公告)号：US07460602B2
公开(公告)日：2008-12-02
申请号：US11119505
申请日：2005-04-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link method is provided, using a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了使用数据驱动器和复制驱动器结构的高速串行链路方法，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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5.发明授权公开(公告)号：US07368902B2
公开(公告)日：2008-05-06
申请号：US11262101
申请日：2005-10-28
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R35/00 , H03K19/003 , G06F19/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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6.发明授权Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection 有权自串式串行链路发射机具有用于振幅，预加重和转换速率控制的分段，以及用于振幅精度和高电压保护的电压调节公开(公告)号：US07307447B2
公开(公告)日：2007-12-11
申请号：US11263138
申请日：2005-10-27
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Todd M. Rasmus
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Todd M. Rasmus
CPC分类号： H03K17/164 , H03K19/018585 , H04L25/0272 , H04L25/0278 , H04L25/028
摘要： A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.
摘要翻译： 一种电路设计方法和发射机，其利用分段自串式终止（SSST）发射机的设计来灵活地控制振幅，预加重和转换速率，该发射机具有双重上拉的多个单独可控段的并行配置， 下拉晶体管。 幅度控制，转换速率控制和预加重控制可以通过对各个段的正常或反相输入进行操作/选择来实现。 还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接（SST）发射器的精确输出的机构。 电源电压的调节允许与传统的串行链路接收器终端电压兼容，并在这些电压大于设备的正常供电时保护发射机输出设备。
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公开(公告)号：US07187206B2
公开(公告)日：2007-03-06
申请号：US10697514
申请日：2003-10-30
IPC分类号： H03K19/0175 , H03H11/26
CPC分类号： H04L25/028 , H03K17/163 , H03K17/164
摘要： Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
摘要翻译： 描述了在串行链路发射机中节省功率的方面。 这些方面包括提供段的并行布置，每个段包括串行链路发射机的预缓冲器和输出级电路，并且每个段独立地使能以实现多个功率电平和多级预加重，同时保持信号中基本恒定的传播延迟 串行链路发射机的路径。 另外的方面包括在预缓冲器级电路中提供旁路路径，以实现段中的可控空闲状态，并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。 还包括在发射机信号路径中提供具有预加重延迟电路的控制元件，以允许预加重延迟电路的最后延迟位的反转，以实现预加重权重的极性改变。
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8.发明授权公开(公告)号：US07570071B2
公开(公告)日：2009-08-04
申请号：US12028451
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28 , G01R35/00 , H03K19/003 , G06F19/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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9.发明申请HIGH SPEED SERIAL LINK OUTPUT STAGE HAVING SELF ADAPTATION FOR VARIOUS IMPAIRMENTS 失效具有各种适应性的自适应高速串行输出级公开(公告)号：US20080285661A1
公开(公告)日：2008-11-20
申请号：US12175846
申请日：2008-07-18
IPC分类号： H04B3/00
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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10.发明申请公开(公告)号：US20080120838A1
公开(公告)日：2008-05-29
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H01R43/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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