公开(公告)号：US20240362031A1

公开(公告)日：2024-10-31

申请号：US18308275

申请日：2023-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  Sai Rahul Chalamalasetti ,  Sergey Serebryakov

IPC: G06F9/445 ,  G06F11/34

CPC classification number: G06F9/44505 ,  G06F11/3495

Abstract: Systems and methods are provided for an accelerator system that includes a baseline (production) accelerator, optimizing accelerator, and control hardware accelerator, and an operation of alternatingly switching the production/optimizing accelerators between production and optimizing. With two production/optimizing accelerators, at any given point in time, one accelerator adapts while another accelerator processes data. Once the second accelerator starts doing a better job (e.g., has adapted to data drift), the accelerators change their modes, and the trainable accelerator becomes the “optimized” one. The accelerators do this non-stop, thus maintaining redundancy, providing expected quality of service (QOS) and adapting to data/concept drift.

公开(公告)号：US20240112029A1

公开(公告)日：2024-04-04

申请号：US18528935

申请日：2023-12-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  John Paul Strachan ,  Sergey Serebryakov

IPC: G06N3/08 ,  G11C13/00

CPC classification number: G06N3/08 ,  G11C13/0069 ,  G11C2213/77

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：US11750629B2

公开(公告)日：2023-09-05

申请号：US17024884

申请日：2020-09-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sergey Serebryakov ,  Tahir Cader ,  Nanjundaiah Deepak

IPC: H04L9/40 ,  H04L43/0817 ,  H04L43/065 ,  H04L43/062 ,  H04L43/04

CPC classification number: H04L63/1425 ,  H04L43/04 ,  H04L43/062 ,  H04L43/065 ,  H04L43/0817 ,  H04L63/20

Abstract: An example device includes processing circuitry and a memory. The memory includes instructions that cause the device to perform various functions. The functions include receiving datastreams from a plurality of sensors of a high performance computing system, classifying each datastream of the each sensor to one of a plurality of datastream models, selecting an anomaly detection algorithm from a plurality of anomaly detection algorithms for each datastream, determining parameters of the each anomaly detection algorithm, determining an anomaly threshold for each datastream, and generating an indication that the sensor associated with the datastream is acting anomalously.

公开(公告)号：US20220067577A1

公开(公告)日：2022-03-03

申请号：US17010744

申请日：2020-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sergey Serebryakov ,  Cong Xu

IPC: G06N20/00

Abstract: Systems and methods are provided for data shuffling for distributed machine learning training, including each training node in the network receiving a shard of training data, wherein the training data set is divided into shards having data items. Each data item is assigned to a working set such that each of the working set includes data items from multiple shards. The training nodes perform training using the data items of a first working set that are in each node's shard. Upon completion of the training using the data items of the first working set, the training nodes performing training using the data items of a second working set that are in their shards; and while the training nodes are performing training on their respective subsets of shards of the second working set, the nodes randomly shuffling data items in the first working set to create a shuffled first working set.

公开(公告)号：US20210201136A1

公开(公告)日：2021-07-01

申请号：US17044633

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  John Paul Strachan ,  Sergey Serebryakov

IPC: G06N3/08 ,  G11C13/00

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：US20200073755A1

公开(公告)日：2020-03-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US20200042287A1

公开(公告)日：2020-02-06

申请号：US16052218

申请日：2018-08-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  Sergey Serebryakov ,  John Paul Strachan

IPC: G06F7/483 ,  G06N3/063 ,  G06N3/08

Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.