公开(公告)号：US07759745B2

公开(公告)日：2010-07-20

申请号：US11656437

申请日：2007-01-23

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/10 ,  H01L29/739

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/115 ,  H01L27/11568 ,  Y10S257/90

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

摘要翻译： 漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b） 浓度高于轻掺杂浅杂质区（7a）的浓度。 轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。 漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

公开(公告)号：US07683440B2

公开(公告)日：2010-03-23

申请号：US11656437

申请日：2007-01-23

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/10 ,  H01L29/739

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

公开(公告)号：US07482226B2

公开(公告)日：2009-01-27

申请号：US11656438

申请日：2007-01-23

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/115 ,  H01L27/11568 ,  Y10S257/90

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

摘要翻译： 漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并在其上掺杂有杂质的重掺杂深杂质区域（7b） 浓度高于轻掺杂浅杂质区（7a）的浓度。 轻掺杂的浅杂质区（7a）导致短沟道效应和编程效率的改善。 漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

公开(公告)号：US06528390B2

公开(公告)日：2003-03-04

申请号：US09798667

申请日：2001-03-02

申请人： Hideki Komori ,  David K. Foote ,  Fei Wang ,  Bharath Rangarajan

发明人： Hideki Komori ,  David K. Foote ,  Fei Wang ,  Bharath Rangarajan

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

公开(公告)号：US06218227B1

公开(公告)日：2001-04-17

申请号：US09426239

申请日：1999-10-25

申请人： Steven K. Park ,  Arvind Halliyal ,  Hideki Komori

发明人： Steven K. Park ,  Arvind Halliyal ,  Hideki Komori

IPC分类号： H01L218238

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A process for fabricating an ONO structure for a MONOS type Flash cell includes growing a first silicon oxide layer over a semiconductor substrate. Thereafter, a silicon nitride layer is formed to overlie the first silicon oxide layer, and a polycrystalline silicon layer is deposited to overlie the silicon nitride layer. By utilizing the polycrystalline silicon layer as the top layer of the ONO structure, a resist layer can be cleaned more aggressively than if the top layer of the ONO structure were an oxide layer. A second silicon oxide layer overlies the polycrystalline layer, of the ONO structure. Since the second silicon oxide layer is deposited on top of polycrystalline silicon after the resist material is cleaned, some resist material can remain on the polycrystalline layer without degrading the performance of the MONOS type cell.

摘要翻译： 用于制造用于MONOS型闪存单元的ONO结构的工艺包括在半导体衬底上生长第一氧化硅层。 此后，形成氮化硅层以覆盖第一氧化硅层，并且沉积多晶硅层以覆盖氮化硅层。 通过利用多晶硅层作为ONO结构的顶层，与ONO结构的顶层是氧化物层相比，可以更积极地清洗抗蚀剂层。 第二氧化硅层覆盖ONO结构的多晶层。 由于在抗蚀剂材料被清洁之后第二氧化硅层沉积在多晶硅的顶部上，所以一些抗蚀剂材料可以保留在多晶层上而不降低MONOS型电池的性能。

公开(公告)号：US06117730A

公开(公告)日：2000-09-12

申请号：US427402

申请日：1999-10-25

申请人： Hideki Komori ,  Kenneth Au ,  Mark Ramsbey

发明人： Hideki Komori ,  Kenneth Au ,  Mark Ramsbey

IPC分类号： H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/11526 ,  H01L27/11546 ,  Y10S438/954

摘要： A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

摘要翻译： 用于制造具有芯和外围的MONOS型闪存单元的ONO结构的工艺包括提供半导体衬底。 生长在半导体衬底上的第一氧化硅层，并且沉积氮化硅层覆盖在氧化硅层上。 在沉积ONO结构的第二氧化硅层之前，执行位线掩模以在芯处形成至少一个位线。 此后，形成ONO掩模以在周边蚀刻期间保护ONO结构。 在沉积和清洁用于位线形成和外围蚀刻的掩模之后，使用HTO沉积工艺沉积第二氧化硅层以覆盖氮化硅层。 通过在形成ONO和位线掩模之后沉积第二氧化硅层，防止第二氧化硅层的劣化，并且顶部氧化硅层保持高质量。

公开(公告)号：US5950086A

公开(公告)日：1999-09-07

申请号：US878119

申请日：1997-06-18

申请人： Satoshi Takahashi ,  Tatsuya Kajita ,  Hideo Kurihara ,  Hideki Komori ,  Masaaki Higashitani

发明人： Satoshi Takahashi ,  Tatsuya Kajita ,  Hideo Kurihara ,  Hideki Komori ,  Masaaki Higashitani

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115

摘要： A semiconductor device is fabricated by the step of forming a first device isolation film in a peripheral circuit region by the use of a first pattern and a second device isolation film in a memory cell region by the use of a second pattern; forming a first conducting film processed by the use of a third pattern having a pattern-to-be-removed in a peripheral edge of the memory cell region; the step of forming an insulation film covering the memory cell region and processed by the use of a fourth pattern whose peripheral edge is positioned on the pattern-to-be-removed of the third pattern; and the step of forming a second conducting film processed by a fifth pattern.

摘要翻译： 通过使用第二图案在存储单元区域中通过使用第一图案和第二器件隔离膜在外围电路区域中形成第一器件隔离膜的步骤来制造半导体器件; 形成通过使用在存储单元区域的外围边缘中具有要去除的图案的第三图案处理的第一导电膜; 形成覆盖存储单元区域并通过使用周边位于第三图案的图案上的第四图案进行处理的绝缘膜的步骤; 以及形成通过第五图案处理的第二导电膜的步骤。