公开(公告)号：US5111136A

公开(公告)日：1992-05-05

申请号：US746148

申请日：1991-08-14

申请人： Hiromi Kawashima

发明人： Hiromi Kawashima

IPC分类号： G01R19/165 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G06F15/78 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  H03K19/00

CPC分类号： G01R31/31701

摘要： A test mode input detection circuit for a semiconductor device comprises a first circuit including a group of transistors and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a transistor whose gate receives an output from the output terminal of the first circuit, and a transistor whose gate receives a power source voltage, these transistors being connected in series between the power source and a ground, a node between the transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.

摘要翻译： 一种用于半导体器件的测试模式输入检测电路包括：第一电路，包括一组晶体管和负载元件，晶体管和负载元件串联连接在电源和输入端之间，晶体管组与 负载元件形成第一电路的输出端子; 第二电路，其包括栅极接收来自第一电路的输出端的输出的晶体管，以及栅极接收电源电压的晶体管，这些晶体管串联连接在电源和地之间，晶体管之间的节点 形成所述第二电路的输出端子; 以及用于响应于第二电路的输出提供测试模式信号的逆变器电路。

公开(公告)号：US4937830A

公开(公告)日：1990-06-26

申请号：US195329

申请日：1988-05-18

申请人： Hiromi Kawashima ,  Ryoji Hagiwara

发明人： Hiromi Kawashima ,  Ryoji Hagiwara

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C16/06 ,  G11C17/00 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device includes a memory cell array; a sense amplifying circuit, operatively connected to the memory cell array, for sensing the information bits and the check bits; a latch circuit, operatively connected to the sense amplifying circuit, for latching the information bits and the check bits sensed by the sense amplifying circuit; and a circuit for correcting an error in logical level in the information bits.The latch circuit latches the logical level of the bit signal at a predetermined time after a change in an address signal. Thus, regardless of whether or not a time at which the logical level of the bit signal of the sense amplifying circuit is settled coincides, the influence is not exerted on the operation of the subsequent error correcting circuit. As a result, it is possible to prevent the appearance of a hazard in the output data and, accordingly, to realize a perfect ECC relief, while increasing a reliability in the reading operation as a device.

公开(公告)号：US4817055A

公开(公告)日：1989-03-28

申请号：US896785

申请日：1986-08-15

申请人： Hideki Arakawa ,  Hiromi Kawashima

发明人： Hideki Arakawa ,  Hiromi Kawashima

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/34 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00 ,  G11C11/40

CPC分类号： G05F3/24 ,  G11C16/30 ,  G11C5/147

摘要： A semiconductor memory circuit includes therein a bias voltage generator which produces a bias voltage to be supplied to a control gate of a field effect transistor (FET) which forms a part of each memory cell in the semiconductor memory circuit. The bias voltage generator is comprised of a bias voltage generating source which is sandwiched by first and second FET's. The second FET operates to stop a driving current flowing through the bias voltage generating source, in a standby mode, and the first FET operates to produce an output voltage near to the bias voltage. The bias voltage is generated by the bias voltage generating source when both the first and second FET's are turned ON, in an active mode, and the driving current flows therethrough.

摘要翻译： 一种半导体存储器电路，其中包括偏置电压发生器，其产生要提供给在半导体存储器电路中形成每个存储单元的一部分的场效应晶体管（FET）的控制栅极的偏置电压。 偏置电压发生器由偏置电压产生源组成，该偏置电压产生源被第一和第二FET夹在中间。 第二FET在待机模式下操作以停止流过偏置电压产生源的驱动电流，并且第一FET工作以产生接近偏置电压的输出电压。 当第一和第二FET在激活模式下都导通时，偏置电压产生源产生偏置电压，并且驱动电流流过其中。