公开(公告)号：US20060197142A1

公开(公告)日：2006-09-07

申请号：US11366479

申请日：2006-03-03

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

公开(公告)号：US20050280065A1

公开(公告)日：2005-12-22

申请号：US11142770

申请日：2005-06-02

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/792

CPC分类号： H01L29/6684 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体之下的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。

公开(公告)号：US06825528B2

公开(公告)日：2004-11-30

申请号：US10149255

申请日：2002-08-12

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US08059080B2

公开(公告)日：2011-11-15

申请号：US11945129

申请日：2007-11-26

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

IPC分类号： G09G3/34

CPC分类号： H01L27/1203 ,  G02F1/13454 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L21/28282 ,  H01L21/84

摘要： To provide a semiconductor storage unit that has a simple structure requiring only a small number of processes to produce, and is provided with a gate insulating film having a memory function. The semiconductor storage unit has a semiconductor layer, two diffusion layer regions forming a source region and a drain region, which are formed on the semiconductor layer, a channel region fixed between the two diffusion layer regions, a gate insulating film that is formed on the channel region, and made of a silicon oxide film containing carbon atoms of 0.1 to 5.0 atomic percent, and a gate electrode formed on the gate insulating film.

摘要翻译： 提供具有仅需要少量工艺制造的简单结构的半导体存储单元，并且设置有具有记忆功能的栅极绝缘膜。 半导体存储单元具有半导体层，形成在半导体层上的源极区和漏极区的两个扩散层区域，固定在两个扩散层区域之间的沟道区域，形成在栅极绝缘膜上的栅极绝缘膜 沟道区域，由碳原子数为0.1〜5.0原子％的氧化硅膜构成，栅极形成在栅极绝缘膜上。

公开(公告)号：US07598559B2

公开(公告)日：2009-10-06

申请号：US11366479

申请日：2006-03-03

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Masayuki Nakano

IPC分类号： H01L29/94

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

摘要翻译： 半导体存储装置具有半导体层，其具有通过第一导电类型区域彼此分离的第一导电类型区域和两个第二导电类型区域，形成在半导体层的表面上的存储功能体和栅极电极。 记忆功能体具有位于电荷存储绝缘体与半导体层之间的电荷存储绝缘体和电荷保持绝缘体，兼作栅极绝缘膜。 电荷保持绝缘体含有这样的杂质原子（磷），使本征半导体成为第二导电类型。

公开(公告)号：US20080136757A1

公开(公告)日：2008-06-12

申请号：US11945129

申请日：2007-11-26

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kohichiro Adachi ,  Masayuki Nakano

IPC分类号： G09G3/36 ,  H01L29/792

CPC分类号： H01L27/1203 ,  G02F1/13454 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L21/28282 ,  H01L21/84

摘要： To provide a semiconductor storage unit that has a simple structure requiring only a small number of processes to produce, and is provided with a gate insulating film having a memory function. The semiconductor storage unit has a semiconductor layer, two diffusion layer regions forming a source region and a drain region, which are formed on the semiconductor layer, a channel region fixed between the two diffusion layer regions, a gate insulating film that is formed on the channel region, and made of a silicon oxide film containing carbon atoms of 0.1 to 5.0 atomic percent, and a gate electrode formed on the gate insulating film.

摘要翻译： 提供具有仅需要少量工艺制造的简单结构的半导体存储单元，并且设置有具有记忆功能的栅极绝缘膜。 半导体存储单元具有半导体层，形成在半导体层上的源极区和漏极区的两个扩散层区域，固定在两个扩散层区域之间的沟道区域，形成在栅极绝缘膜上的栅极绝缘膜 沟道区域，由碳原子数为0.1〜5.0原子％的氧化硅膜构成，栅极形成在栅极绝缘膜上。

公开(公告)号：US20070090430A1

公开(公告)日：2007-04-26

申请号：US11581352

申请日：2006-10-17

申请人： Masayuki Nakano ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Masayuki Nakano ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/94 ,  H01L29/788 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7923 ,  H01L27/11568

摘要： semiconductor memory device comprising: a semiconductor layer; a gate electrode formed on the semiconductor layer through a gate insulating film; a channel region provided beneath the gate electrode; source/drain diffusion regions having a conductivity type opposite to that of the channel region and provided on both sides of the channel region; and memory function bodies having a function of holding a charge and formed on at least both sides of the gate electrode, wherein the memory function body is formed of a charge holding film and a tunnel insulating film, the tunnel insulating film exists on the side wall portion of the gate electrode and between the charge holding film and the semiconductor layer, and the tunnel insulating film between the charge holding film and the semiconductor layer is thicker than the tunnel insulating film between the charge holding film and the side wall portion of the gate electrode.

摘要翻译： 半导体存储器件包括：半导体层; 通过栅极绝缘膜形成在半导体层上的栅电极; 设置在栅电极下方的沟道区; 源极/漏极扩散区域，其具有与沟道区域的导电类型相反的导电类型，并且设置在沟道区域的两侧; 以及具有保持电荷并形成在所述栅电极的至少两侧上的功能的记忆功能体，其中所述记忆功能体由电荷保持膜和隧道绝缘膜形成，所述隧道绝缘膜存在于所述侧壁 栅电极的一部分和电荷保持膜与半导体层之间，电荷保持膜与半导体层之间的隧道绝缘膜比电荷保持膜与栅极侧壁部之间的隧道绝缘膜厚 电极。

公开(公告)号：US07176526B2

公开(公告)日：2007-02-13

申请号：US10899183

申请日：2004-07-27

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106。 源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US06515340B2

公开(公告)日：2003-02-04

申请号：US09917954

申请日：2001-07-31

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2257 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78654

摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

公开(公告)号：US06426532B1

公开(公告)日：2002-07-30

申请号：US09720714

申请日：2001-04-19

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L31119

CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。