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公开(公告)号：US06291861B1
公开(公告)日：2001-09-18
申请号：US09345414
申请日：1999-06-30
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/2257 , H01L27/088 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4941 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/78654
摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
摘要翻译： 具有器件分离区域和有源区域的半导体器件包括栅极氧化膜，源极/漏极区域和电耦合到源极/漏极区域的电极。 有源区在第一面处与栅极氧化膜接触，源/漏区的一部分位于第一面的上方。 电极在第二面处与源极/漏极区域接触，第二面部相对于第一面构成一个角度。
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公开(公告)号：US06682966B2
公开(公告)日：2004-01-27
申请号：US10171540
申请日：2002-06-17
IPC分类号： A01L2100
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.
摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。
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3.发明授权Semiconductor device, method of manufacture thereof, and information processing device 失效半导体装置及其制造方法以及信息处理装置公开(公告)号：US06825528B2
公开(公告)日：2004-11-30
申请号：US10149255
申请日：2002-08-12
IPC分类号： H01L2976
CPC分类号： H01L29/66628 , H01L21/2251 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/7834 , H01L29/78657
摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.
摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。
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4.发明授权Method for producing FET with source/drain region occupies a reduced area 失效具有源极/漏极区域的FET的制造方法占据了减小的面积公开(公告)号：US06656799B2
公开(公告)日：2003-12-02
申请号：US10322492
申请日：2002-12-19
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/2257 , H01L27/088 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4941 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/78654
摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
摘要翻译： 具有器件分离区域和有源区域的半导体器件包括栅极氧化膜，源极/漏极区域和电耦合到源极/漏极区域的电极。 有源区在第一面处与栅极氧化膜接触，源/漏区的一部分位于第一面的上方。 电极在第二面处与源极/漏极区域接触，第二面部相对于第一面构成一个角度。
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5.发明授权Semiconductor device, method for producing the same, and information processing apparatus 有权半导体装置及其制造方法以及信息处理装置公开(公告)号：US07176526B2
公开(公告)日：2007-02-13
申请号：US10899183
申请日：2004-07-27
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/2251 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/7834 , H01L29/78657
摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.
摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106。 源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。
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公开(公告)号：US06515340B2
公开(公告)日：2003-02-04
申请号：US09917954
申请日：2001-07-31
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/2257 , H01L27/088 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4941 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/78654
摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
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公开(公告)号：US06426532B1
公开(公告)日：2002-07-30
申请号：US09720714
申请日：2001-04-19
IPC分类号： H01L31119
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.
摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。
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公开(公告)号：US20090073158A1
公开(公告)日：2009-03-19
申请号：US12212303
申请日：2008-09-17
申请人： Kotaro Kataoka , Hiroshi Iwata , Yoshiji Ohta , Kenji Kimoto , Kenji Komiya , Kouichiro Adachi , Akihide Shibata , Masatomi Harada
发明人： Kotaro Kataoka , Hiroshi Iwata , Yoshiji Ohta , Kenji Kimoto , Kenji Komiya , Kouichiro Adachi , Akihide Shibata , Masatomi Harada
IPC分类号： G09G5/00 , H01L29/792 , G05F1/10
CPC分类号： H01L29/792 , H01L29/66833
摘要： A memory element having a large memory window and a high reliability is provided at low cost by performing high speed write and erase operations at a relatively low voltage and suppressing rewrite degradation. A memory element includes a semiconductor layer arranged on an insulating substrate, a first diffusion layer region and a second diffusion layer region having a conductivity type of P-type, a charge accumulating film for covering a channel region between the first diffusion layer region and the second diffusion layer region and being injected with charges from the channel region, and a gate electrode positioned on a side opposite to the channel region with the charge accumulating film in between.
摘要翻译： 通过在相对低的电压下执行高速写入和擦除操作并且抑制重写劣化，以低成本提供具有大存储器窗口和高可靠性的存储元件。 存储元件包括布置在绝缘基板上的半导体层，具有P型导电类型的第一扩散层区域和第二扩散层区域，用于覆盖第一扩散层区域和第二扩散层区域之间的沟道区域的电荷累积膜 第二扩散层区域，并且从沟道区域注入电荷，以及位于与沟道区相反的一侧的栅电极，电荷积聚膜在其间。
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公开(公告)号：US5733820A
公开(公告)日：1998-03-31
申请号：US637349
申请日：1996-04-24
IPC分类号： G01N21/68 , H01J37/32 , H01L21/3065 , H01L21/00
CPC分类号： H01J37/32192 , G01N21/68 , H01J37/32678 , H01J37/32935 , H01J37/32972 , H01L21/3065 , H01J2237/3346
摘要： Silicon material layers formed on an oxide underlayer are attached using a plasma including a gas mixture of a halogen and oxygen. Intensities of first emissions from the plasma at a first wavelength and second emissions from the plasma at a second wavelength are measured. A ratio of the first emissions intensity to the second emissions intensity is determined. The selectivity of silicon layers to oxide underlayers is measured for various conditions of the plasma under which the emissions intensity ratio is obtained. A correlation between the emissions intensity ratio and the selectivity is then established for various etching parameters. A plasma condition to obtain a desired selectivity may then be appropriately set using the established correlation.
摘要翻译： 使用包含卤素和氧气的混合物的等离子体，在氧化物底层上形成的硅材料层附着。 测量来自第一波长的等离子体的第一次发射的强度和来自第二波长的等离子体的第二次发射。 确定第一排放强度与第二排放强度的比值。 在获得发射强度比的等离子体的各种条件下测量硅层对氧化物底层的选择性。 然后针对各种蚀刻参数确定发射强度比和选择性之间的相关性。 然后可以使用建立的相关性来适当地设置获得期望选择性的等离子体条件。
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公开(公告)号：US6074568A
公开(公告)日：2000-06-13
申请号：US2707
申请日：1998-01-05
IPC分类号： G01N21/68 , H01J37/32 , H01L21/3065 , G01L21/30
CPC分类号： H01J37/32192 , G01N21/68 , H01J37/32678 , H01J37/32935 , H01J37/32972 , H01L21/3065 , H01J2237/3346
摘要： A method for diagnosing a function of plasma etching apparatuses and a method for estimating selectivity in an actual etching process in fabrication of semiconductor devices involves generating plasma of a gas mixture including halogen and oxygen in a predetermined condition. An intensity of one of first emissions from the plasma at a first wavelength and an intensity of one of second emissions from the plasma at a second wavelength is measured A ratio of the intensity of the one of first emissions to that of the one of second emissions is obtained. The obtained emission intensity ratio is compared with an emission intensity ratio which is previously measured for a plasma condition when the plasma etching apparatus operates normally.
摘要翻译： 用于诊断等离子体蚀刻装置的功能的方法和用于在半导体装置的制造中的实际蚀刻工艺中估计选择性的方法包括在预定条件下产生包括卤素和氧的气体混合物的等离子体。 测量来自第一波长的等离子体的第一次发射的强度和来自第二波长的等离子体的第二次发射的强度之一的强度是第一发射的强度与第二发射中的一个的强度的比值 获得。 将所获得的发光强度比与等离子体蚀刻装置正常工作时的等离子体状态预先测定的发光强度比进行比较。
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