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    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD
    21.
    发明申请
    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD 有权
    计算机系统和计算机系统控制方法

    公开(公告)号：US20120117407A1

    公开(公告)日：2012-05-10

    申请号：US13310892

    申请日：2011-12-05

    申请人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    发明人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data.The second memory accepts read and write operations while operating at the third power consumption.

    摘要翻译： 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

    RANDOM NUMBER GENERATOR
    23.
    发明申请
    RANDOM NUMBER GENERATOR 失效
    随机数发电机

    公开(公告)号：US20120026784A1

    公开(公告)日：2012-02-02

    申请号：US13205737

    申请日：2011-08-09

    申请人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    发明人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    IPC分类号： G11C11/00

    CPC分类号： G06F7/588 ,  H04L9/0866

    摘要： According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state.

    摘要翻译： 根据实施例的一个方面，提供一种包括至少一个磁隧道结（MTJ）元件和控制电路的随机数产生电路。 MTJ元件对应于第一逻辑值进入高电阻状态，并且也进入与不同于第一逻辑值的第二逻辑值相对应的低电阻状态。 当MTJ元件处于高电阻状态时，控制电路向MTJ元件提供第一电流，用于将MTJ元件从高电阻状态随机反向到低电阻状态，并且向MTJ元件提供用于随机反转的第二电流 当MTJ元件处于低电阻状态时，MTJ元件从低电阻状态到高电阻状态。

    Storage apparatus including non-volatile SRAM
    24.
    发明授权
    Storage apparatus including non-volatile SRAM 有权
    存储设备包括非易失性SRAM

    公开(公告)号：US07903451B2

    公开(公告)日：2011-03-08

    申请号：US12404510

    申请日：2009-03-16

    申请人： Yutaka Yamada ,  Tatsunori Kanai ,  Masaya Tarui ,  Keiko Abe

    发明人： Yutaka Yamada ,  Tatsunori Kanai ,  Masaya Tarui ,  Keiko Abe

    IPC分类号： G11C11/00

    CPC分类号： G11C13/00 ,  G11C11/1659 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0069 ,  G11C14/0081 ,  G11C2013/0073

    摘要： According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having a third state and a fourth state, wherein the first storage element is brought into the first state when a current flows from the first storage element to the first storage element and is brought into the second state when the current flows from the first storage element to the first storage element, wherein the second storage element is brought into the fourth state when a current flows from the second storage element to the second storage element and is brought into the third state when the current flows from the second storage element to the second storage element.

    摘要翻译： 根据一个实施例，一种存储装置包括：第一反相器; 第二个逆变器; 具有第一状态和第二状态的第一存储元件; 以及具有第三状态和第四状态的第二存储元件，其中当电流从第一存储元件流向第一存储元件时，第一存储元件处于第一状态，并且当电流流动时处于第二状态 从第一存储元件到第一存储元件，其中当电流从第二存储元件流到第二存储元件时，第二存储元件处于第四状态，并且当电流从第二存储元件 存储元件到第二存储元件。

    Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand
    25.
    发明授权
    Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand 有权
    当等待按需访问第二个较慢的非易失性存储器时，将处理器和存储器切换到省电模式

    公开(公告)号：US08683249B2

    公开(公告)日：2014-03-25

    申请号：US13310892

    申请日：2011-12-05

    申请人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    发明人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.

    摘要翻译： 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

    Random number generator
    26.
    发明授权
    Random number generator 失效
    随机数发生器

    公开(公告)号：US08374021B2

    公开(公告)日：2013-02-12

    申请号：US13205737

    申请日：2011-08-09

    申请人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    发明人： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    IPC分类号： G11C11/00

    CPC分类号： G06F7/588 ,  H04L9/0866

    摘要： According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state.

    摘要翻译： 根据实施例的一个方面，提供一种包括至少一个磁隧道结（MTJ）元件和控制电路的随机数产生电路。 MTJ元件对应于第一逻辑值进入高电阻状态，并且也进入与不同于第一逻辑值的第二逻辑值相对应的低电阻状态。 当MTJ元件处于高电阻状态时，控制电路向MTJ元件提供第一电流，用于将MTJ元件从高电阻状态随机反向到低电阻状态，并且向MTJ元件提供用于随机反转的第二电流 当MTJ元件处于低电阻状态时，MTJ元件从低电阻状态到高电阻状态。