公开(公告)号：US09003128B2

公开(公告)日：2015-04-07

申请号：US13234837

申请日：2011-09-16

Applicant: Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

Inventor： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0897 ,  G06F12/123 ,  G06F2212/225 ,  Y02D10/13

Abstract: According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

Abstract translation: 根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联 比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。 在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中 记忆。

公开(公告)号：US08866443B2

公开(公告)日：2014-10-21

申请号：US13059253

申请日：2011-01-17

Applicant: Keiko Abe ,  Yasuhiro Kobayashi ,  Masahiro Watanabe ,  Hisaaki Takabayashi ,  Yoshikazu Hirose ,  Shinichi Sano ,  Ichiro Shimoura

Inventor： Keiko Abe ,  Yasuhiro Kobayashi ,  Masahiro Watanabe ,  Hisaaki Takabayashi ,  Yoshikazu Hirose ,  Shinichi Sano ,  Ichiro Shimoura

IPC: H02J7/00 ,  H02J7/14 ,  G01R31/36 ,  H01M10/44

CPC classification number: G01R31/3651 ,  G01R31/3624 ,  G01R31/3679

Abstract: The life of a lead acid storage battery is extended by changing an over-frequency equalized charge interval performed on a lead acid storage battery, in accordance with a transition situation of a state of charge (SOC) of the lead acid storage battery. The lead acid storage battery is also made to be advantageous in terms of cost by reducing the equalized charge with a low degree of urgency to reduce the power and cost for equalized charge, and by reducing the number of stops of a natural energy storage system. A lead acid storage battery and a lead acid storage battery system whose operational management can be easily performed are achieved by a method in which the future timing when the equalized charge is performed can be grasped by people operating the lead acid storage battery.

Abstract translation: 根据铅酸蓄电池的充电状态（SOC）的转变情况，通过改变在铅酸蓄电池上执行的超频均衡充电间隔来延长铅酸蓄电池的寿命。 铅酸蓄电池还通过以低的紧迫程度减少均衡充电以降低均衡充电的功率和成本以及减少自然能量存储系统的停止次数而在成本方面是有利的。 可以通过这样的方法实现其操作管理可以容易地执行的铅酸蓄电池和铅酸蓄电池系统，其中当进行均衡充电的未来时间可以由操作铅酸蓄电池的人掌握。

公开(公告)号：US20130055189A1

公开(公告)日：2013-02-28

申请号：US13561483

申请日：2012-07-30

Applicant: Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

Inventor： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

Abstract translation: 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

公开(公告)号：US20130041142A1

公开(公告)日：2013-02-14

申请号：US13512687

申请日：2010-09-08

Applicant: Keiko Abe ,  Takumi Misaka ,  Satoshi Fujiwara

Inventor： Keiko Abe ,  Takumi Misaka ,  Satoshi Fujiwara

IPC: C07H3/04 ,  C07C69/76 ,  C07C43/23 ,  C07C235/46 ,  C07C235/34 ,  C07C49/707 ,  C07D309/40 ,  C07C309/63

CPC classification number: G01N33/502 ,  A23L27/30 ,  A23L27/39 ,  C07K14/705 ,  G01N2333/726

Abstract: [Object] An object of the present invention is to provide a human sweet taste receptor-acting sweet taste regulating substance to a sweet taste substance by which the advantageous effects such as improvement in a taste, saving of a sweetener, reduction in calorie, low caries etc. can be obtained by applying to various foods and beverages.[Solution] The sweet taste receptor-acting sweet taste regulating substance of the present invention is identified by measurement of a physiological response by a sweet taste substance, using a cultured cell strain which is allowed to express hT1R2 and hT1R3, and a G protein α subunit, by transferring an expression construct obtained by inserting respective cDNAs encoding the hT1R2 and the hT1R3, and the G protein α subunit into the same plasmid, into a 293 cell in which an FRT (Flippase Recognition Target) site has been incorporated into one place in a genome DNA.

Abstract translation: 本发明的目的在于提供一种甜味调味物质的甜味调理物质，其具有甜味物质的改善，甜味剂的节省，热量的降低，低热量等有益效果 龋齿等可以通过适用于各种食品和饮料而获得。 [解决方案]本发明的甜味受体作用甜​​味调节物质通过使用允许表达hT1R2和hT1R3的培养细胞株和G蛋白α测定甜味物质的生理反应来鉴定 通过将通过将编码hT1R2和hT1R3的各个cDNA和G蛋白α亚基插入相同质粒而获得的表达构建体转移到其中已经将FRT（翻转酶识别靶位点）结合到一个位置的293细胞中 在基因组DNA。

公开(公告)号：US20130031397A1

公开(公告)日：2013-01-31

申请号：US13421090

申请日：2012-03-15

Applicant: Keiko Abe ,  Shinobu Fujita

Inventor： Keiko Abe ,  Shinobu Fujita

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

Abstract: One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register.

Abstract translation: 一个实施例提供一种包括处理器的信息处理设备; 记忆块 连接到存储块的内部电压发生器; 连接到存储器块的输入/输出电路; 对应于内部电压发生器，输入/输出电路和存储器块的每个安装开关，并被配置为用电源来切换连接的ON / OFF; 数据寄存器，被配置为存储控制开关的ON / OFF的数据组; 以及数据管理电路，被配置为将数据集合设置在数据寄存器中，其中当输入到处理器的时钟信号变为OFF时，数据管理电路产生第一类型的数据组，其将接通的开关 内部电压发生器和断开连接到存储器块的开关，并将数据集的第一种类型设置在数据寄存器中。

公开(公告)号：US20130027093A1

公开(公告)日：2013-01-31

申请号：US13461101

申请日：2012-05-01

Applicant: Hiroki NOGUCHI ,  Keiko Abe ,  Shinichi Yasuda ,  Shinobu Fujita

Inventor： Hiroki NOGUCHI ,  Keiko Abe ,  Shinichi Yasuda ,  Shinobu Fujita

IPC: H03L7/08 ,  H03B19/00

CPC classification number: H03L7/14 ,  H03L2207/18

Abstract: One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.

Abstract translation: 一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值 电阻值高于第一电阻值。

公开(公告)号：US20120235705A1

公开(公告)日：2012-09-20

申请号：US13419205

申请日：2012-03-13

Applicant: Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

Inventor： Keiko Abe ,  Shinichi Yasuda ,  Kumiko Nomura ,  Shinobu Fujita

IPC: H03K19/177 ,  G11C16/04

CPC classification number: H03K19/1776 ,  G11C11/412 ,  G11C14/0063

Abstract: According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.

Abstract translation: 根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有 连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极 低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极 电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

公开(公告)号：US20120142145A1

公开(公告)日：2012-06-07

申请号：US13369427

申请日：2012-02-09

Applicant: Keiko Abe

Inventor： Keiko Abe

IPC: H01L21/50

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.

Abstract translation: 根据一个实施例，一种半导体器件制造方法包括：制造具有电极的第一衬底，产生具有通孔的第二衬底，将第二衬底堆叠在第一衬底上，绝缘层介于第一衬底和第二衬底之间 通过用第二基板作为掩模蚀刻绝缘层，在通孔下方的绝缘层中到达电极的孔，并且用导电物质填充通孔和孔。

公开(公告)号：US20110309881A1

公开(公告)日：2011-12-22

申请号：US13223898

申请日：2011-09-01

Applicant: Shinichi Yasuda ,  Keiko Abe ,  Shinobu Fujita

Inventor： Shinichi Yasuda ,  Keiko Abe ,  Shinobu Fujita

IPC: H01L25/065

CPC classification number: H03K19/20 ,  G11C5/02 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.

Abstract translation: 根据一个实施例，三维半导体集成电路包括堆叠的第一，第二和第三芯片，以及将第一，第二和第三芯片彼此连接的公共导体。 第一芯片包括第一多电平电路，第二芯片包括第二多电平电路，第三芯片包括解码电路。 第一多电平电路包括输入二进制第一数据并输出第一和第二电位之一的第一反相器和连接在第一反相器的输出端和公共导体之间的第一电容器。 第二多电平电路包括输入二进制第二数据并输出第三和第四电位之一的第二反相器和连接在第二反相器的输出端和公共导体之间的第二电容器。

公开(公告)号：US08043851B2

公开(公告)日：2011-10-25

申请号：US12896676

申请日：2010-10-01

Applicant: Keiko Abe ,  Tomiko Asakura ,  Hiroyuki Sorimachi ,  Tazuko Uenoyama ,  Kenichiro Nakajima ,  Katsuhiko Kitamoto ,  Junichi Maruyama ,  Mikiya Kishi

Inventor： Keiko Abe ,  Tomiko Asakura ,  Hiroyuki Sorimachi ,  Tazuko Uenoyama ,  Kenichiro Nakajima ,  Katsuhiko Kitamoto ,  Junichi Maruyama ,  Mikiya Kishi

IPC: C12N15/00 ,  C07H21/02

CPC classification number: C07K14/47 ,  A23L27/31

Abstract: Disclosed is a polypeptide shown in the following in (A), and a protein dimer neoculin comprising the polypeptide Neoculin Acidic Subunit (NAS) and the polypeptide Neoculin Basic Subunit (NBS) and having a taste-modifying activity: (A) a polypeptide comprising an amino acid sequence shown in SEQ ID NO.2 in the sequence listing.

Abstract translation: 公开了以下（A）中所示的多肽和包含多肽新霉素酸性亚基（NAS）和多肽新霉素基础亚基（NBS）并具有调味活性的蛋白质二聚体新霉素：（A）包含 序列表中SEQ ID NO：2所示的氨基酸序列。