公开(公告)号：US5538904A

公开(公告)日：1996-07-23

申请号：US310397

申请日：1994-09-22

申请人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

发明人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

IPC分类号： H01L21/66 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L21/76251 ,  Y10S148/012

摘要： A method of estimating the amount of boron on the surface of silicone samples in which a plurality of reference samples shallowly ion-implanted with boron in different dosages are prepared and heat-treated under the same conditions of temperature and time as are used in a bonding heat treatment to obtain the bonded wafer, thereafter, the boron profile in the direction of the depth of the bonding interface in each reference sample is measured using a SIMS and compared with an actual boron profile at the bonding interface of a bonded wafer to be estimated so as to determine one reference sample whose boron profile is equivalent to the actual boron profile of the bonded wafer to be estimated, and finally a dosage of boron in the determined reference sample is estimated by convertion to be a surface density of boron presenting at the bonding interface of the bonded wafer to be estimated at an initial stage prior to the bonding heat treatment of the bonded wafer to be estimated. Thus, the boron profile obtained by SIMS measurement can be converted into the boron surface density with the result that the boron quantity at the bonding interface of a bonded wafer can be readily estimated to be a boron surface density.

摘要翻译： 一种估计硅胶样品表面上硼的量的方法，其中以与不同剂量的硼浅离子注入的多个参考样品制备并在与粘合中使用的相同的温度和时间条件下进行热处理 热处理以获得接合的晶片，此后，使用SIMS测量每个参考样品中的接合界面的深度方向上的硼分布，并与待估计的键合晶片的键合界面处的实际硼分布进行比较 以便确定一个参考样品，其硼分布等于要估计的键合晶片的实际硼分布，最后通过转换来估计所确定的参考样品中的硼剂量，使其为硼的表面密度 接合晶片的接合界面在待估计的接合晶片的接合热处理之前的初始阶段被估计。 因此，通过SIMS测量获得的硼分布可以转化为硼表面密度，结果是接合晶片的键合界面处的硼量可以容易地估计为硼表面密度。

公开(公告)号：US5478408A

公开(公告)日：1995-12-26

申请号：US408798

申请日：1995-03-23

申请人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

发明人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  H01L21/322 ,  H01L27/12 ,  H01L21/265

CPC分类号： H01L21/2007 ,  H01L21/3225 ,  Y10S148/012

摘要： There is provided an SOI (Silicon On Insulator) substrate having a thick SOI layer, where crystallographic defects mainly consisting of OSFs (Oxidation Induced Stacking Fault) are practically prevented from occurrence in the SOI layer, according to the present invention.The manufacturing method for the SOI substrate according to the present invention comprises the following steps of: the silicon oxide film being formed by thermal oxidation on the surface of a first silicon wafer having a concentration of interstitial oxygen under 16 ppma (per JEIDA Standard); the first silicon wafer being superimposed on a second silicon wafer, which is a support for supporting the first silicon wafer, with the silicon oxide film sandwiched therebetween; then the superimposed wafers being heat-treated so as to obtain a bonded wafer; and further the bulk of the first silicon wafer of the bonded wafer being reduced by grinding and then polishing so as to obtain the SOI substrate with the SOI layer of more than 5 .mu.m in thickness, which is a single crystal layer, formed on the second silicon wafer.

摘要翻译： 根据本发明，提供了具有厚SOI层的SOI（绝缘体上硅）衬底，其中实际上防止了在SOI层中出现主要由OSF（氧化诱发堆叠故障）组成的晶体缺陷。 根据本发明的SOI衬底的制造方法包括以下步骤：在具有16ppma（根据JEIDA标准）的间隙氧浓度的第一硅晶片的表面上通过热氧化形成氧化硅膜; 所述第一硅晶片叠加在第二硅晶片上，所述第二硅晶片是用于支撑所述第一硅晶片的支撑体，其间夹置有所述氧化硅膜; 然后对叠加的晶片进行热处理以获得接合晶片; 并且通过研磨然后抛光来还原接合晶片的第一硅晶片的大部分，以获得厚度大于5μm的SOI层（其是形成在单晶层上的单晶层）的SOI衬底 第二硅晶片。

公开(公告)号：US5393370A

公开(公告)日：1995-02-28

申请号：US139849

申请日：1993-10-22

申请人： Yutaka Ohta ,  Masatake Katayama ,  Isao Moroga

发明人： Yutaka Ohta ,  Masatake Katayama ,  Isao Moroga

IPC分类号： H01L21/302 ,  G01B11/06 ,  H01L21/3065 ,  H01L21/66 ,  H01L21/762 ,  H01L27/12 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： G01B11/0683 ,  H01L21/3065 ,  H01L21/76251 ,  H01L22/12 ,  H01L22/20 ,  Y10S438/977

摘要： To provide a method of making a SOI film having a more uniform thickness in a SOI substrate which makes it possible to keep the variance at .+-.0.3 micrometers or less throughout the entire surface of the substrate, even for SOI substrates with a SOI film thickness between 1 micrometer and 10 micrometers. The surface of a SOI substrate is divided into a plurality of sections, then the SOI film thickness is measured for each section Wi (i=1-n) by means of the spectral interference method using an optical fiber cable, and, simultaneously, the SOI film is etched down to a prescribed thickness by a dry etching device, and thus a desired value and a variance (.+-.0.3 micrometers) of the SOI film thickness is obtained.

摘要翻译： 为了提供在SOI衬底中制造具有更均匀厚度的SOI膜的方法，其使得可以在衬底的整个表面上将偏差保持在+/- 0.3微米或更小，即使对于具有SOI膜的SOI衬底 厚度介于1微米至10微米之间。 SOI衬底的表面被分成多个部分，然后通过使用光纤电缆的光谱干涉法测量每个部分Wi（i = 1-n）的SOI膜厚度，同时， 通过干蚀刻装置将SOI膜蚀刻到规定的厚度，从而获得SOI膜厚度的期望值和方差（+/- 0.3微米）。

公开(公告)号：US5336634A

公开(公告)日：1994-08-09

申请号：US25256

申请日：1993-03-02

申请人： Masatake Katayama ,  Makoto Sato ,  Yutaka Ohta ,  Mitsuru Sugita ,  Konomu Ohki

发明人： Masatake Katayama ,  Makoto Sato ,  Yutaka Ohta ,  Mitsuru Sugita ,  Konomu Ohki

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L21/763 ,  H01L21/76

CPC分类号： H01L21/30608 ,  H01L21/3083 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/05

摘要： A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.

摘要翻译： 介电隔离的衬底由单晶硅衬底或接合衬底和结合在一起的复合结构中的单晶硅衬底或基底衬底构成。 接合衬底具有（110）面作为主晶面并且设置有垂直壁壁的护城河和邻近护城河定位的基本上平方的岛。 使用特定掩模图案的各向异性蚀刻产生护城河和岛屿。 还公开了一种复合结构的制造方法。