公开(公告)号：US06695482B2

公开(公告)日：2004-02-24

申请号：US10025576

申请日：2001-12-26

申请人： Masayuki Niwa ,  Yoshitaka Ito ,  Mitsuru Sugita ,  Akira Ono ,  Susumu Mamiya ,  Masaaki Sakamoto

发明人： Masayuki Niwa ,  Yoshitaka Ito ,  Mitsuru Sugita ,  Akira Ono ,  Susumu Mamiya ,  Masaaki Sakamoto

IPC分类号： F16C3310

CPC分类号： F16C33/1065 ,  F16C9/02 ,  F16C17/022 ,  F16C2240/40 ,  F16C2240/42

摘要： A half bearing constituting a cylindrical plain bearing for supporting a shaft for rotation when two of the half bearings are combined together. The half bearing has two circumferential ends each of which has a plurality of circumferential grooves without formation of any crush relief surface. The grooves extend substantially over an overall circumferential dimension of the half bearing and include portions located at both circumferential ends of the half bearing respectively. Each portion has a larger axially sectional area than the grooves formed in a portion of the half bearing mainly subjected to load during rotation of the shaft.

摘要翻译： 构成圆柱形滑动轴承的半轴承，用于当两个半轴承组合在一起时支撑转轴的转动。 半轴承具有两个周向端部，每个端部具有多个周向槽，而不形成任何挤压面。 凹槽基本上在半轴承的整个圆周尺寸上延伸并且包括分别位于半轴承的两个圆周端部的部分。 每个部分具有比在轴的旋转期间主要承受载荷的半轴承的部分中形成的槽更大的轴向截面面积。

公开(公告)号：US5542051A

公开(公告)日：1996-07-30

申请号：US202247

申请日：1994-02-25

申请人： Mitsuru Sugita ,  Yurika Sumida

发明人： Mitsuru Sugita ,  Yurika Sumida

IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F11/34 ,  G11B27/00

CPC分类号： G06F11/0757

摘要： A watch don timer comprising a reload register 2 and a shift register 3 is disclosed. In the case where an object to be monitored is operating normally, a circuit 43 is supplied with as a reload request signal the rising timing of a monitor signal changing cyclically, which is reloaded from the reload register 2 of the shift, register 3 in synchronism with a reload request signal in accordance with the value of data located in each bit of the shift register 3. Circuits 41, 42 are adapted to detect an abnormal condition in the case where a reload request signal is given in a cycle shorter or longer than a predetermined cycle of reloading. This configuration realizes a watch dog timer with a comparatively small scale of circuit configuration in which the pulse width of the input signal is monitored, the cycle detected and the execution of a plurality of instructions monitored, while at the same time having a programmable width and cycle and a tolerable range thereof.

摘要翻译： 公开了一种包括重载寄存器2和移位寄存器3的监视定时器。 在要监视的对象正常工作的情况下，电路43作为重新加载请求信号被提供，周期地改变监视信号的上升定时，其从移位寄存器3的重载寄存器2同步重新加载 具有根据位于移位寄存器3的每个位中的数据的值的重新加载请求信号。电路41,42适于在以更短或更长的周期中给出重新加载请求信号的情况下检测异常状况 预定的重新加载循环。 该配置实现了具有比较小规模的电路配置的看门狗定时器，其中监视输入信号的脉冲宽度，检测周期和监视多个指令的执行，同时具有可编程宽度和 循环和其可容许的范围。

公开(公告)号：US5506994A

公开(公告)日：1996-04-09

申请号：US49720

申请日：1993-04-20

申请人： Mitsuru Sugita

发明人： Mitsuru Sugita

IPC分类号： G06F15/167 ,  G06F15/78 ,  G06F13/00 ,  G06F15/16

CPC分类号： G06F15/7814

摘要： A multiprocessor-type one-chip microcomputer, of the type having a plurality of processors, each having a separate address space, a plurality of programmable ROMs, for storing program data for each processor, and a set of functional terminals, with the microcomputer including a common writing bus and a control means for coupling either the common writing bus or a set of functional lines to the functional terminals based on the setting of a mode setting signal. During normal operations the functional lines are coupled to the functional terminals and each programmable ROM is accessed by a processor using addresses in the address space of the processor. When new instruction data is to be written to the programmable ROMs, the common writing bus is coupled to the functional terminals and instruction data is written to the programmable ROMs using addresses in a common address space.

摘要翻译： 一种具有多个处理器的类型的多处理器型单片机，每个具有单独的地址空间，用于存储每个处理器的程序数据的多个可编程ROM和一组功能终端，其中微型计算机包括 公共写入总线和用于根据模式设置信号的设置将公共写入总线或一组功能线耦合到功能终端的控制装置。 在正常操作期间，功能线耦合到功能端子，并且处理器使用处理器的地址空间中的地址来访问每个可编程ROM。 当新的指令数据要写入可编程ROM时，公共写入总线与功能端子耦合，并且使用公共地址空间中的地址将指令数据写入可编程ROM。

公开(公告)号：US5276842A

公开(公告)日：1994-01-04

申请号：US682826

申请日：1991-04-09

申请人： Mitsuru Sugita

发明人： Mitsuru Sugita

IPC分类号： G11C11/41 ,  G06F13/16 ,  G06F15/167 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F15/167 ,  G06F13/1663

摘要： A dual port memory 50 comprises two decoders 9a, 9b, and two sense amplifiers 14a, 14b, associated with a memory cell array 100. The dual port memory 50 can be accessed by a CPU 6 of the A system side and a CPU 7 of the B system side simultaneously. The occurrence of contention between the accesses of CPUs 6 and 7 with respect to the same memory cell is detected by an access contention detecting circuit 51. In response to contention detection, a control signal generating circuit 52 generates various control signals. The A port side and B port side of the dual port memory 50 each is provided with write data latches 53a, 53b, read data latches 54a, 54b, switches 55a-57b, select switches 58a, 58b, and tri-state buffers 59a and 59b, respectively, to perform arbitration all the time of access contention, in accordance with the control signal from control signal generating circuit 52.

摘要翻译： 双端口存储器50包括与存储单元阵列100相关联的两个解码器9a，9b和两个读出放大器14a，14b。双端口存储器50可由A系统侧的CPU 6和 B系统侧同时。 CPU6和7相对于相同存储单元的访问之间的争用由访问争用检测电路51检测。响应于争用检测，控制信号产生电路52产生各种控制信号。 双端口存储器50的A端口侧和B端口侧各自设置有写数据锁存器53a，53b，读数据锁存器54a，54b，开关55a-57b，选择开关58a，58b和三态缓冲器59a和 59b分别根据来自控制信号发生电路52的控制信号执行访问争用的所有时间。

公开(公告)号：US5243606A

公开(公告)日：1993-09-07

申请号：US455489

申请日：1989-12-21

申请人： Mitsuru Sugita ,  Kikuo Muramatsu

发明人： Mitsuru Sugita ,  Kikuo Muramatsu

IPC分类号： G06F11/30 ,  G05B9/02 ,  G05B23/02 ,  G06F11/00 ,  G06F15/78

CPC分类号： G06F11/0751 ,  G05B9/02 ,  G06F11/0757

摘要： The microcomputer of the invention comprises a flip-flop which repeats setting and resetting of a monitor signal. The monitor signal is delivered from an external device in response to a PWM output signal for driving the external device. The flip-flop sets and resets at the front edge, of the monitor signal. The invention detects a failure of the external device according to the presence or absence of inversion of its held value. Hence, the failure of the external device operating at high speeds can be reliably detected by the microcomputer of the invention.

摘要翻译： 本发明的微型计算机包括重复监视信号的设置和复位的触发器。 响应于用于驱动外部设备的PWM输出信号，监视信号从外部设备传送。 触发器在前端设置和复位监视器信号。 本发明根据其持有值的存在或不存在来检测外部设备的故障。 因此，本发明的微型计算机能够可靠地检测高速运转的外部装置的故障。

公开(公告)号：USRE39613E1

公开(公告)日：2007-05-08

申请号：US11303090

申请日：2005-12-16

申请人： Masayuki Niwa ,  Yoshitaka Ito ,  Mitsuru Sugita ,  Akira Ono ,  Susumu Mamiya ,  Masaaki Sakamoto

发明人： Masayuki Niwa ,  Yoshitaka Ito ,  Mitsuru Sugita ,  Akira Ono ,  Susumu Mamiya ,  Masaaki Sakamoto

IPC分类号： F16C33/10

CPC分类号： F16C33/1065 ,  F16C9/02 ,  F16C17/022 ,  F16C2240/40 ,  F16C2240/42

摘要： A half bearing constituting a cylindrical plain bearing for supporting a shaft for rotation when two of the half bearings are combined together. The half bearing has two circumferential ends each of which has a plurality of circumferential grooves without formation of any crush relief surface. The grooves extend substantially over an overall circumferential dimension of the half bearing and include portions located at both circumferential ends of the half bearing respectively. Each portion has a larger axially sectional area than the grooves formed in a portion of the half bearing mainly subjected to load during rotation of the shaft.

摘要翻译： 构成圆柱形滑动轴承的半轴承，用于当两个半轴承组合在一起时支撑转轴的转动。 半轴承具有两个周向端部，每个端部具有多个周向槽，而不形成任何挤压面。 凹槽基本上在半轴承的整个圆周尺寸上延伸并且包括分别位于半轴承的两个圆周端部的部分。 每个部分具有比在轴的旋转期间主要承受载荷的半轴承的部分中形成的槽更大的轴向截面面积。

公开(公告)号：US5700093A

公开(公告)日：1997-12-23

申请号：US797245

申请日：1997-02-07

申请人： Nobutaka Hiramatsu ,  Mitsuru Sugita ,  Yoshikazu Mizuno ,  Takayuki Shibayama

发明人： Nobutaka Hiramatsu ,  Mitsuru Sugita ,  Yoshikazu Mizuno ,  Takayuki Shibayama

IPC分类号： F16C33/12 ,  F16C9/04 ,  F16C17/24 ,  F16C33/08 ,  F16C33/20 ,  F16C35/02

CPC分类号： F16C9/04 ,  F16C17/24 ,  F16C33/08 ,  F16C33/20 ,  Y10S384/907

摘要： Disclosed is a bearing structure of a sliding bearing which is held in a housing and which rotatably supports a rotary shaft. At least one of the outer surface of the sliding bearing and the inner surface of the housing is covered with a coating layer which essentially consists of, by weight, a total amount of not more than 90% of solid lubricant and hard particles in which the solid lubricant is of 3 to 50% and the hard particles are of 1 to 50%, and the balance of polyamideimide resin.

摘要翻译： 公开了一种滑动轴承的轴承结构，其被保持在壳体中并且可旋转地支撑旋转轴。 滑动轴承的外表面和壳体的内表面中的至少一个被覆层覆盖，该涂层基本上由重量的不超过90％的固体润滑剂和硬颗粒组成，其中 固体润滑剂为3〜50％，硬质粒子为1〜50％，余量为聚酰胺酰亚胺树脂。

公开(公告)号：US5349564A

公开(公告)日：1994-09-20

申请号：US731556

申请日：1991-07-17

申请人： Takashi Miyake ,  Mitsuru Sugita

发明人： Takashi Miyake ,  Mitsuru Sugita

IPC分类号： G11C11/401 ,  G06F12/00 ,  G06F13/24 ,  G11B7/00

CPC分类号： G06F13/24

摘要： A multi-port RAM has a decoding portion for decoding a plurality of specific addresses for generating interruptions and a selection circuit for selecting some addresses from among the plurality of specific addresses. Since the plurality of addresses are selected for generating interruptions in parallel or in the sequence of time for each generation of an interruption, the data processing capability at the time of generation of interruptions can be improved.

摘要翻译： 多端口RAM具有用于解码多个特定地址以产生中断的解码部分和用于从多个特定地址中选择一些地址的选择电路。 由于多个地址被选择用于产生每次产生中断的并行或时间序列的中断，所以可以提高产生中断时的数据处理能力。

公开(公告)号：US5336634A

公开(公告)日：1994-08-09

申请号：US25256

申请日：1993-03-02

申请人： Masatake Katayama ,  Makoto Sato ,  Yutaka Ohta ,  Mitsuru Sugita ,  Konomu Ohki

发明人： Masatake Katayama ,  Makoto Sato ,  Yutaka Ohta ,  Mitsuru Sugita ,  Konomu Ohki

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L21/763 ,  H01L21/76

CPC分类号： H01L21/30608 ,  H01L21/3083 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/05

摘要： A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.

摘要翻译： 介电隔离的衬底由单晶硅衬底或接合衬底和结合在一起的复合结构中的单晶硅衬底或基底衬底构成。 接合衬底具有（110）面作为主晶面并且设置有垂直壁壁的护城河和邻近护城河定位的基本上平方的岛。 使用特定掩模图案的各向异性蚀刻产生护城河和岛屿。 还公开了一种复合结构的制造方法。

公开(公告)号：US06959365B2

公开(公告)日：2005-10-25

申请号：US10138567

申请日：2002-05-06

申请人： Naoki Ootani ,  Yoshio Kasai ,  Toshihiro Abe ,  Mitsuru Sugita

发明人： Naoki Ootani ,  Yoshio Kasai ,  Toshihiro Abe ,  Mitsuru Sugita

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F15/78

CPC分类号： G06F12/0246

摘要： A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

摘要翻译： 获得具有内置闪存的微型计算机，其中闪存可以被保存在闪速存储器上的重写程序适当地重写，而不需要额外的复杂控制电路。 在接受构成重写命令的擦除/写入命令时，闪速存储器模块（2）在执行一系列处理期间向闪速存储器控制电路（3）输出表示忙状态的就绪状态信号RYIBY。 当就绪状态信号RYIBY表示忙碌状态时，闪速存储器控制电路（3）将保持信号HOLD输出为“H”，以阻止CPU（1）访问闪存模块（2）。 当就绪状态信号RYIBY恢复就绪状态时，闪速存储器控制电路（3）将保持信号HOLD输出为“L”，以允许CPU（1）访问闪存模块（2）。