公开(公告)号：US07986545B2

公开(公告)日：2011-07-26

申请号：US12465125

申请日：2009-05-13

申请人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/025

摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

摘要翻译： 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 耦合在多个位线和多个可变电阻之间的多个选择晶体管被设置。

公开(公告)号：US20110121390A1

公开(公告)日：2011-05-26

申请号：US12929455

申请日：2011-01-26

申请人： Won-joo Kim ,  Tae-hee Lee ,  Dae-kil Cha ,  Yoon-dong Park

发明人： Won-joo Kim ,  Tae-hee Lee ,  Dae-kil Cha ,  Yoon-dong Park

IPC分类号： H01L27/12

CPC分类号： H01L29/7841

摘要： Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.

公开(公告)号：US07813180B2

公开(公告)日：2010-10-12

申请号：US12005376

申请日：2007-12-27

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C7/00

CPC分类号： H01L29/7881 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.

摘要翻译： 示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。 示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。 第一电荷存储层可以在半导体衬底和第一控制栅电极之间。 源区域可以在第一控制栅电极的一侧的半导体衬底中限定。 第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。 第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。 位线可以连接到第一漏区。

公开(公告)号：US20100133600A1

公开(公告)日：2010-06-03

申请号：US12591686

申请日：2009-11-30

申请人： Won-joo Kim ,  Sang-moo Choi ,  Tae-hee Lee ,  Yoon-dong Park ,  Dae-kil Cha

发明人： Won-joo Kim ,  Sang-moo Choi ,  Tae-hee Lee ,  Yoon-dong Park ,  Dae-kil Cha

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7881 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof.

摘要翻译： 具有改善的感测余量的一个晶体管（1-T）动态随机存取存储器（DRAM），其相对独立于存储在其身体区域中的载体的量。

公开(公告)号：US20100038719A1

公开(公告)日：2010-02-18

申请号：US12461131

申请日：2009-07-31

申请人： Won-Joo Kim ,  Tae-hee Lee ,  Yoon-dong Park ,  Sang-moo Choi ,  Dae-kll Cha

发明人： Won-Joo Kim ,  Tae-hee Lee ,  Yoon-dong Park ,  Sang-moo Choi ,  Dae-kll Cha

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0688 ,  H01L27/108 ,  H01L27/10882

摘要： Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other.

摘要翻译： 公开半导体装置及其制造方法。 根据该方法，用于制造具有多个层的半导体装置的操作次数可以与制造具有一层的半导体装置的操作次数相同。 半导体装置可以包括在相同方向上并联延伸的第一有源区，彼此分离，并且包括彼此在第一有源区的相对端上的第一和第二杂质掺杂区。 半导体装置还可以包括在第一有源区上方的层上的与第一有源区相同方向的第二有源区，该第一有源区平行彼此分开，并且包括第一和第二杂质掺杂区， 第二活跃区域。

公开(公告)号：US20090212364A1

公开(公告)日：2009-08-27

申请号：US12219360

申请日：2008-07-21

申请人： Won-joo Kim ,  Tae-hee Lee ,  Dae-kil Cha ,  Yoon-dong Park

发明人： Won-joo Kim ,  Tae-hee Lee ,  Dae-kil Cha ,  Yoon-dong Park

IPC分类号： H01L27/12 ,  H01L21/00

CPC分类号： H01L29/7841

摘要： Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.

摘要翻译： 提供半导体基板及其制造方法。 半导体衬底包括衬底区域，绝缘区域和浮体区域。 绝缘区域设置在基板区域上。 浮体区域通过绝缘区域与基板区域分离，并且设置在绝缘区域上。 基板区域和浮体区域由具有相同特性的材料形成。 制造半导体衬底的方法包括通过蚀刻大块衬底形成至少一个浮体图案，通过蚀刻浮体图案的下部中间部分将本体衬底分离成衬底区域和浮体区域，以及填充绝缘体 在浮体区域和衬底区域之间的材料。

公开(公告)号：US20090212320A1

公开(公告)日：2009-08-27

申请号：US12219990

申请日：2008-07-31

申请人： Won-joo Kim ,  Dae-kil Cha ,  Tae-hee Lee ,  Yoon-dong Park

发明人： Won-joo Kim ,  Dae-kil Cha ,  Tae-hee Lee ,  Yoon-dong Park

IPC分类号： H01L29/739

CPC分类号： H01L29/7391 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/8618

摘要： Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions.

摘要翻译： 提供包括其的半导体器件和半导体器件。 半导体器件包括设置在半导体衬底上的主体区域，设置在半导体衬底上并位于体区域的相对侧上的栅极图案，以及设置在身体区域的上表面上的第一和第二杂质掺杂区域。 栅极图案可以与第一和第二杂质掺杂区域分开或大于期望的距离，使得栅极图案在垂直于第一和第二杂质的方向上不与第一和第二杂质掺杂区域重叠 掺杂区域。

公开(公告)号：US20080175061A1

公开(公告)日：2008-07-24

申请号：US12005376

申请日：2007-12-27

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.

摘要翻译： 示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。 示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。 第一电荷存储层可以在半导体衬底和第一控制栅电极之间。 源区域可以在第一控制栅电极的一侧的半导体衬底中限定。 第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。 第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。 位线可以连接到第一漏区。

公开(公告)号：US08258542B2

公开(公告)日：2012-09-04

申请号：US12219990

申请日：2008-07-31

申请人： Won-joo Kim ,  Dae-kil Cha ,  Tae-hee Lee ,  Yoon-dong Park

发明人： Won-joo Kim ,  Dae-kil Cha ,  Tae-hee Lee ,  Yoon-dong Park

IPC分类号： H01L29/66

CPC分类号： H01L29/7391 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/8618

摘要： Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions.

摘要翻译： 提供包括其的半导体器件和半导体器件。 半导体器件包括设置在半导体衬底上的主体区域，设置在半导体衬底上并位于体区域的相对侧上的栅极图案，以及设置在身体区域的上表面上的第一和第二杂质掺杂区域。 栅极图案可以与第一和第二杂质掺杂区域分开或大于期望的距离，使得栅极图案在垂直于第一和第二杂质的方向上不与第一和第二杂质掺杂区域重叠 掺杂区域。

公开(公告)号：US07796432B2

公开(公告)日：2010-09-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。