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    Semiconductor apparatuses and methods of manufacturing the same
    1.
    发明申请
    Semiconductor apparatuses and methods of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20100038719A1

    公开(公告)日：2010-02-18

    申请号：US12461131

    申请日：2009-07-31

    申请人： Won-Joo Kim ,  Tae-hee Lee ,  Yoon-dong Park ,  Sang-moo Choi ,  Dae-kll Cha

    发明人： Won-Joo Kim ,  Tae-hee Lee ,  Yoon-dong Park ,  Sang-moo Choi ,  Dae-kll Cha

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L27/0688 ,  H01L27/108 ,  H01L27/10882

    摘要： Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other.

    摘要翻译： 公开半导体装置及其制造方法。 根据该方法，用于制造具有多个层的半导体装置的操作次数可以与制造具有一层的半导体装置的操作次数相同。 半导体装置可以包括在相同方向上并联延伸的第一有源区，彼此分离，并且包括彼此在第一有源区的相对端上的第一和第二杂质掺杂区。 半导体装置还可以包括在第一有源区上方的层上的与第一有源区相同方向的第二有源区，该第一有源区平行彼此分开，并且包括第一和第二杂质掺杂区， 第二活跃区域。

    Non-volatile memory devices and methods of operating and fabricating the same
    3.
    发明申请
    Non-volatile memory devices and methods of operating and fabricating the same 审中-公开
    非易失性存储器件及其操作和制造方法

    公开(公告)号：US20080191264A1

    公开(公告)日：2008-08-14

    申请号：US12010139

    申请日：2008-01-22

    申请人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

    发明人： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

    IPC分类号： H01L29/00 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

    摘要翻译： 提供了使用基于氧化物的化合物半导体高度集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括一个或多个基于氧化物的化合物半导体层。 多个辅助栅极电极可以布置成与一个或多个氧化物基化合物半导体层绝缘。 多个控制栅电极可以位于与多个辅助栅极电极不同的多个辅助栅电极的相邻对之间。 多个控制栅电极可以与一个或多个氧化物基化合物半导体层绝缘。 可以在一个或多个氧化物基化合物半导体层和多个控制栅电极之间插入多个电荷存储层。

    Memory device including resistance change layer as storage node and method(s) for making the same
    5.
    发明授权
    Memory device including resistance change layer as storage node and method(s) for making the same 有权
    存储器件包括作为存储节点的电阻变化层及其制造方法

    公开(公告)号：US07507674B2

    公开(公告)日：2009-03-24

    申请号：US11270565

    申请日：2005-11-10

    申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    IPC分类号： H01L21/461

    CPC分类号： H01L27/24 ,  Y10S438/947

    摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.

    摘要翻译： 提供一种用于制造包括根据本发明的示例性实施例的作为存储节点的电阻变化层的存储器件的方法和由该方法制造的存储器件。 根据本发明的示例性实施例，该方法可以包括在底层上层叠（顺序地或以其他方式）导电材料层，二极管层和数据存储层，在数据存储层上形成第一材料层，形成 第一孔暴露第一材料层中的数据存储层，在第一孔的侧壁上形成具有第二材料层的第一间隔物，用第三材料层填充第一孔并覆盖第一间隔物; 去除所述第一材料层，在所述第一间隔物的侧壁上形成具有第四材料层的第二间隔物; 去除第三材料层，并且使用第一和第二间隔件作为掩模，形成以第一堆叠结构暴露底层的第二孔。 这些操作可能导致如所描述的位线和字线的形成。

    Memory device including resistance change layer as storage node and method(s) for making the same
    7.
    发明申请
    Memory device including resistance change layer as storage node and method(s) for making the same 有权

    公开(公告)号：US20060110877A1

    公开(公告)日：2006-05-25

    申请号：US11270565

    申请日：2005-11-10

    申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/24 ,  Y10S438/947

    摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.

    Wire-type semiconductor devices and methods of fabricating the same
    8.
    发明授权
    Wire-type semiconductor devices and methods of fabricating the same 有权
    线型半导体器件及其制造方法

    公开(公告)号：US07663166B2

    公开(公告)日：2010-02-16

    申请号：US11723074

    申请日：2007-03-16

    申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

    发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

    IPC分类号： H01L27/088

    CPC分类号： H01L29/0657 ,  H01L29/42392 ,  H01L29/78696

    摘要： Provided are relatively higher-performance wire-type semiconductor devices and relatively economical methods of fabricating the same. A wire-type semiconductor device may include at least one pair of support pillars protruding above a semiconductor substrate, at least one fin protruding above the semiconductor substrate and having ends connected to the at least one pair of support pillars, at least one semiconductor wire having ends connected to the at least one pair of support pillars and being separated from the at least one fin, a common gate electrode surrounding the surface of the at least one semiconductor wire, and a gate insulating layer between the at least one semiconductor wire and the common gate electrode.

    摘要翻译： 提供了相对较高性能的线型半导体器件和相对经济的制造方法。 线型半导体器件可以包括突出在半导体衬底上方的至少一对支撑柱，至少一个突出于半导体衬底之上并具有连接到至少一对支撑柱的端子的鳍片，至少一个半导体线材具有 连接到所述至少一对支撑柱并且与所述至少一个鳍分离的端部，围绕所述至少一个半导体线的表面的公共栅电极以及所述至少一个半导体线和所述至少一个半导体线之间的栅极绝缘层 共栅电极。

    NAND-type nonvolatile memory devices having common bit lines and methods of operating the same
    10.
    发明申请
    NAND-type nonvolatile memory devices having common bit lines and methods of operating the same 审中-公开
    具有公共位线的NAND型非易失性存储器件及其操作方法

    公开(公告)号：US20070183204A1

    公开(公告)日：2007-08-09

    申请号：US11657652

    申请日：2007-01-25

    申请人： Suk-Pil Kim ,  Won-Joo Kim ,  Yoon-Dong Park ,  Jae-Woong Hyun ,  Jung-Hoon Lee

    发明人： Suk-Pil Kim ,  Won-Joo Kim ,  Yoon-Dong Park ,  Jae-Woong Hyun ,  Jung-Hoon Lee

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C7/18

    摘要： A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.

    摘要翻译： NAND型非易失性存储器件包括第一串和第二串。 第一和第二串中的每一个的端部分别连接到公共位线和公共源极线。 第一串和第二串中的每一个具有串选择晶体管，多个单元器件和源极选择晶体管。 字线分别连接到相同行中的单元设备的控制栅极。 第一串选择线和第二串选择线分别连接到第一串和第二串的串选择晶体管的栅极。 第一源选择线和第二源选择线分别连接到第一串和第二串的栅极。