公开(公告)号：US20140054547A1

公开(公告)日：2014-02-27

申请号：US13914514

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/78

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US09064702B2

公开(公告)日：2015-06-23

申请号：US13956273

申请日：2013-07-31

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。

公开(公告)号：US09006705B2

公开(公告)日：2015-04-14

申请号：US13914514

申请日：2013-06-10

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/778 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  B82Y10/00

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US20140038426A1

公开(公告)日：2014-02-06

申请号：US13956273

申请日：2013-07-31

Applicant: Globalfoundries Inc. ,  IMEC

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/02

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。