公开(公告)号：US20140077332A1

公开(公告)日：2014-03-20

申请号：US14024820

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Brunco

IPC: H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract translation: 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。

公开(公告)号：US08963225B2

公开(公告)日：2015-02-24

申请号：US14024820

申请日：2013-09-12

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract translation: 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。

公开(公告)号：US09006705B2

公开(公告)日：2015-04-14

申请号：US13914514

申请日：2013-06-10

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/778 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  B82Y10/00

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US09029217B1

公开(公告)日：2015-05-12

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GlobalFoundries Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L21/336 ,  H01L29/94 ,  H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20150126010A1

公开(公告)日：2015-05-07

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20140054547A1

公开(公告)日：2014-02-27

申请号：US13914514

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/78

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。

公开(公告)号：US20240371874A1

公开(公告)日：2024-11-07

申请号：US18688594

申请日：2021-09-03

Applicant: IMEC VZW ,  HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Amita Rawat ,  Hao Wu ,  Geert Hellings ,  Krishna Kumar Bhuwalka

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A nanostructure according to the present disclosure comprises a pair of nanosheet or nanowire transistors configured to conduct charge by carriers of opposite polarity (such as n and p type carriers), wherein one of the pair of transistors is provided with inner spacers and the other is not provided with inner spacers. Depending on the type of charge carrier, the omission of the inner spacers may improve the admittance of the device. This is demonstrated in an example embodiment comprising a Si-channel PMOS nanosheet transistor. Conversely, in a Si-channel NMOS nanosheet transistor, the omission of the inner spacers has a negative effect on the parasitic capacitance that outweighs some of the benefits of the inner spacer omission. An example embodiment of the present disclosure includes complementary NMOS and PMOS silicon transistors, wherein the NMOS is provided with inner spacers and the PMOS is not provided with inner spacers.

公开(公告)号：US20230178629A1

公开(公告)日：2023-06-08

申请号：US18060945

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Geert Hellings ,  Bilal Chehab ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545

Abstract: A method is provided for forming a FET device. The method includes: forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure; forming a mask line; forming along a first side of the fin structure a source and drain trench in the deposited layer; forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench; forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities; embedding the mask line in a cover material and removing the mask structure; forming a gate trench by etching the dummy structure; forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US20250157914A1

公开(公告)日：2025-05-15

申请号：US18946788

申请日：2024-11-13

Applicant: Imec vzw

Inventor： James Edward Myers ,  Geert Hellings

IPC: H01L23/50 ,  G06F1/10

Abstract: An integrated circuit device includes a clock distribution network that includes a clock mesh formed by first clock lines and second clock lines. The first clock lines and the second clock lines are arranged at the same level in a backside interconnect structure of the integrated circuit device and are interconnected by crossing each other.

公开(公告)号：US08698129B2

公开(公告)日：2014-04-15

申请号：US13723149

申请日：2012-12-20

Applicant: IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

Inventor： Geert Hellings ,  Geert Eneman

IPC: H01L29/06

CPC classification number: H01L29/7782 ,  H01L29/0623 ,  H01L29/36

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract translation: 一种无植入物量子阱晶体管，其中所述掺杂区域包括相对于所述衬底的相邻区域的掺杂剂的浓度具有增加的掺杂剂浓度的注入区域，所述注入区域基本上位于所述量子阱区域的相对侧 门区域。