公开(公告)号：US11741189B2

公开(公告)日：2023-08-29

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G11C11/412 ,  G06F17/16

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20210397675A1

公开(公告)日：2021-12-23

申请号：US17013646

申请日：2020-09-06

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

公开(公告)号：US20210257017A1

公开(公告)日：2021-08-19

申请号：US16850016

申请日：2020-04-16

Applicant: Industrial Technology Research Institute

Inventor： Fu-Cheng Tsai ,  Heng-Yuan Lee ,  Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/56

Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

公开(公告)号：US10324054B2

公开(公告)日：2019-06-18

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

公开(公告)号：US20190154473A1

公开(公告)日：2019-05-23

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US10101175B2

公开(公告)日：2018-10-16

申请号：US15607389

申请日：2017-05-26

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shyh-Shyuan Sheu ,  Ya-Wen Yang ,  Chih-Ping Cheng ,  Chih-Sheng Lin

IPC: G01D3/02 ,  G01D18/00 ,  H03K17/30

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

公开(公告)号：US20170122892A1

公开(公告)日：2017-05-04

申请号：US14961906

申请日：2015-12-08

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/121 ,  G01N27/127

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

公开(公告)号：US09136843B2

公开(公告)日：2015-09-15

申请号：US14447531

申请日：2014-07-30

Applicant: Industrial Technology Research Institute

Inventor： Pei-Ling Tseng ,  Keng-Li Su ,  Chih-Sheng Lin ,  Shyh-Shyuan Sheu

IPC: H03K19/00 ,  H03K19/003 ,  G01R31/28 ,  H01L21/66

CPC classification number: H03K19/003 ,  G01R31/28 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.

Abstract translation: 半导体器件的TSV修复电路包括第一芯片，第二芯片，至少两个TSV，至少两个数据路径电路和输出逻辑电路。 每个数据路径电路包括输入驱动电路，TSV检测电路，存储器件，保护电路和功率控制电路。 TSV检测电路检测TSV状态，存储器件保持TSV状态，保护电路根据TSV状态确定是否将TSV的第一端拉至接地电压，并且功率控制电路防止漏电流 来自基板的电源电压。