System and method for dividing the carrier center frequency of an rf modulated signal by a non-integer divisor

    公开(公告)号:US11057062B2

    公开(公告)日:2021-07-06

    申请号:US16842629

    申请日:2020-04-07

    Abstract: An example method according to some embodiments includes receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.

    MULTI-STAGE LNA WITH REDUCED MUTUAL COUPLING
    22.
    发明申请

    公开(公告)号:US20200280293A1

    公开(公告)日:2020-09-03

    申请号:US16811883

    申请日:2020-03-06

    Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.

    MULTI-STAGE LNA WITH REDUCED MUTUAL COUPLING
    23.
    发明申请

    公开(公告)号:US20200083857A1

    公开(公告)日:2020-03-12

    申请号:US16125480

    申请日:2018-09-07

    Applicant: Innophase Inc.

    Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.

    Polar receiver system and method for Bluetooth communications

    公开(公告)号:US10122397B2

    公开(公告)日:2018-11-06

    申请号:US15655676

    申请日:2017-07-20

    Abstract: Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

    Polar receiver signal processing apparatus and methods
    27.
    发明授权
    Polar receiver signal processing apparatus and methods 有权
    极地接收机信号处理装置和方法

    公开(公告)号:US09264282B2

    公开(公告)日:2016-02-16

    申请号:US13839557

    申请日:2013-03-15

    CPC classification number: H04L27/389 H04L27/3818

    Abstract: A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit.

    Abstract translation: 一种从提供相位导数信号和包络幅度信号的极坐标接收机产生同相和正交信号的方法,包括接收估计的相位导数信号; 产生估计相位信号; 将估计的相位信号映射到角度值; 基于角度值将所估计的相位信号转换为同相信号和正交信号; 并向解调电路提供同相信号和正交信号。

    Single-bit direct modulation transmitter
    28.
    发明授权
    Single-bit direct modulation transmitter 有权
    单位直接调制发射机

    公开(公告)号:US09020066B2

    公开(公告)日:2015-04-28

    申请号:US13842470

    申请日:2013-03-15

    CPC classification number: H04L25/03834 H03M1/685 H04L25/0384 H04L27/34

    Abstract: Single-bit transmitter modulator having a digital pulse shaping filter configured to shape data pulses of an inphase signal and quadrature signal; an upsampling filter configured to increase the sample rate of the inphase signal and quadrature signal; a sigma-delta modulator providing a one-bit inphase output signal and a one-bit quadrature output signal; an inphase low-order analog low pass filter coupling the one-bit inphase output signal to an inphase channel input of a quadrature modulator, and a quadrature low-order analog low pass filter coupling the one-bit quadrature output signal to a quadrature channel input of a quadrature modulator; and, wherein the quadrature modulator is connected to a carrier signal generator and is configured to generate an inphase and quadrature modulated carrier.

    Abstract translation: 具有数字脉冲整形滤波器的单位发射调制器,被配置为对同相信号和正交信号的数据脉冲进行整形; 上采样滤波器,被配置为增加同相信号和正交信号的采样率; 提供一位同相输出信号和一位正交输出信号的Σ-Δ调制器; 将一位同相输出信号耦合到正交调制器的同相通道输入的同相低阶模拟低通滤波器,以及正交低阶模拟低通滤波器,将一位正交输出信号耦合到正交通道输入 的正交调制器; 并且其中所述正交调制器连接到载波信号发生器并被配置为产生同相和正交调制载波。

    Receiver architecture and methods for demodulating binary phase shift keying signals
    29.
    发明授权
    Receiver architecture and methods for demodulating binary phase shift keying signals 有权
    用于解调二进制相移键控信号的接收机架构和方法

    公开(公告)号:US08705663B2

    公开(公告)日:2014-04-22

    申请号:US14034426

    申请日:2013-09-23

    Applicant: Innophase Inc.

    Inventor: Yang Xu

    CPC classification number: H04L27/2272 H04L27/2071 H04L27/22

    Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

    Abstract translation: 描述接收机。 接收机包括第一注入锁定振荡器,其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。 接收机还包括第二注入锁定振荡器,其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。 此外,接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 并且,第二锁相环与第二注入锁定振荡器的第四输入耦合。 第二锁相环被配置为产生第二频率参考。

    Receiver Architecture and Methods for Demodulating Binary Phase Shift Keying Signals
    30.
    发明申请
    Receiver Architecture and Methods for Demodulating Binary Phase Shift Keying Signals 有权
    用于解调二进制相移键控信号的接收机架构和方法

    公开(公告)号:US20130195223A1

    公开(公告)日:2013-08-01

    申请号:US13754819

    申请日:2013-01-30

    Applicant: Innophase Inc.

    Inventor: Yang Xu

    CPC classification number: H04L27/2272 H04L27/2071 H04L27/22

    Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

    Abstract translation: 描述接收机。 接收机包括第一注入锁定振荡器,其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。 接收机还包括第二注入锁定振荡器,其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。 此外,接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 并且,第二锁相环与第二注入锁定振荡器的第四输入耦合。 第二锁相环被配置为产生第二频率参考。

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