TECHNIQUES FOR ANALOG MULTIBIT DATA REPRESENTATION FOR IN-MEMORY COMPUTING

    公开(公告)号:US20220406392A1

    公开(公告)日:2022-12-22

    申请号:US17353493

    申请日:2021-06-21

    Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

    BAYESIAN NEURAL NETWORK AND METHODS AND APPARATUS TO OPERATE THE SAME

    公开(公告)号:US20210034947A1

    公开(公告)日:2021-02-04

    申请号:US17075527

    申请日:2020-10-20

    Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

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