公开(公告)号：US20230198510A1

公开(公告)日：2023-06-22

申请号：US17558056

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Amy Whitcombe ,  Somnath Kundu ,  Brent R. Carlton

IPC: H03K4/94 ,  H03K5/01 ,  H03F3/45 ,  H03K19/20

CPC classification number: H03K4/94 ,  H03K5/01 ,  H03F3/45475 ,  H03K19/20

Abstract: A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

公开(公告)号：US20240111346A1

公开(公告)日：2024-04-04

申请号：US17957052

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Amy Whitcombe ,  Finbarr O'Regan ,  Conor O'Keeffe ,  Sundar Krishnamurthy

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: An apparatus can include at least two circuit portions having separate power sequencer circuitry. The apparatus can further include processing circuitry configured to control at least one portion of the at least two circuit portions to operate at an initial low power level and subsequent higher power levels to full operation.

公开(公告)号：US20230018398A1

公开(公告)日：2023-01-19

申请号：US17342397

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Amy Whitcombe ,  Brent Carlton

IPC: G04F10/00 ,  H03M1/38 ,  G05F1/575

Abstract: A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

公开(公告)号：US12189344B2

公开(公告)日：2025-01-07

申请号：US17342397

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Amy Whitcombe ,  Brent Carlton

IPC: G04F10/00 ,  G05F1/575 ,  H03K19/20 ,  H03M1/38

Abstract: A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.