公开(公告)号：US20230285999A1

公开(公告)日：2023-09-14

申请号：US17694302

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Paul Diglio ,  Jiraporn Seangatith

IPC: B05B7/14 ,  B05B7/16

CPC classification number: B05B7/1486 ,  B05B7/1626

Abstract: Cold-spray nozzles, systems, and techniques are described herein related to manufacturing implementations of efficient film deposition. A deposition system includes multiple feed systems to deliver solid powder materials at controlled feed rates and temperatures, and a nozzle, including convergent and divergent sections and connections to the feed systems, to receive a carrier fluid in the convergent section and to spray the carrier fluid and the solid powder materials out of the divergent section. A nozzle includes multiple ports to receive solid powder materials for admission into a carrier fluid, with one or more ports in the convergent section and one or more ports in the divergent section. A method may include delivering a carrier fluid to a nozzle, heating multiple solid powder materials, delivering these solid powder materials to the nozzle, and spraying the solid powder materials out of a divergent section of the nozzle.

公开(公告)号：US20230099827A1

公开(公告)日：2023-03-30

申请号：US17484281

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Wenhao Li ,  Stephen Morein ,  Yoshihiro Tomita

IPC: H01L23/532 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098020A1

公开(公告)日：2023-03-30

申请号：US17484384

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch ,  Adel Elsherbini ,  Thomas L. Sounart ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/50 ,  H05K7/20 ,  H01L23/31

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220415837A1

公开(公告)日：2022-12-29

申请号：US17359380

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff ,  Johanna Swan ,  Julien Sebot

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

公开(公告)号：US11417586B2

公开(公告)日：2022-08-16

申请号：US16141746

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/498 ,  H01L21/48 ,  H01L23/427 ,  H01L25/065 ,  H01L23/00

Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and at least one heat transfer fluid conduit extending through the substrate, wherein the heat transfer fluid conduit is electrically attached to the at least one integrated circuit device. In one embodiment, the at least one heat transfer fluid conduit is a power transfer route for the at least one integrated circuit device.

公开(公告)号：US11387161B2

公开(公告)日：2022-07-12

申请号：US16651329

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid

IPC: H01L23/367 ,  H01L23/42

Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.

公开(公告)号：US20220199546A1

公开(公告)日：2022-06-23

申请号：US17127382

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Gerald S. Pasdast ,  Kimin Jun ,  Zhiguo Qian ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Feras Eid ,  Kevin P. O'Brien ,  Han Wui Then

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

公开(公告)号：US20220199450A1

公开(公告)日：2022-06-23

申请号：US17132429

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Michael J. Baker ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/67

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

公开(公告)号：US11329358B2

公开(公告)日：2022-05-10

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.