公开(公告)号：US11107920B2

公开(公告)日：2021-08-31

申请号：US16509421

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32 ,  H01L29/165

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US10573750B2

公开(公告)日：2020-02-25

申请号：US15779485

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US11769836B2

公开(公告)日：2023-09-26

申请号：US16405807

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Tahir Ghani ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

公开(公告)号：US20230207655A1

公开(公告)日：2023-06-29

申请号：US17561915

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Rushabh D. Shah ,  Glenn Glass ,  Mohammad R. Hasan ,  Anand Murthy ,  Cory C. Bomberger

IPC: H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/456 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/7851

Abstract: Cap layers are formed on silicon germanium (SiGe) source/drain regions to provide etch resistance to processing steps that can occur in a semiconductor manufacturing process between formation of the SiGe source/drain regions and metal contact formation. The cap layers comprise boron and are thin (e.g., 2 nm or less) to provide for a low metal contact resistance. The atomic concentration of boron in the second layer is in a range of about 0.2-20%. In addition to providing etch resistance, the cap layer provides for a thermally stable contact resistance as the cap layer can prevent or limit the creation of voids in the SiGe layer by preventing or limiting the diffusion of germanium from the SiGe layer into the metal in subsequent annealing and other high-temperature processing steps.

公开(公告)号：US20230170420A1

公开(公告)日：2023-06-01

申请号：US17536725

申请日：2021-11-29

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Prashant Majhi ,  Glenn Glass

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/7849 ,  H01L29/78696 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/045 ,  H01L29/7848 ,  H01L29/0673

Abstract: A gate-all-around transistor device includes a substrate, and a layer over the substrate, where the layer includes an insulator material. The device also includes a source region and a drain region, and a body that includes a semiconductor material over the layer and that laterally extends between the source and drain regions. In an example, the semiconductor material of the body is under biaxial tensile strain induced by an underlying strained semiconductor on insulator (SSOI) structure, in addition to any additional strain induced by the source and drain regions (if any). A gate structure is at least in part wrapped around the body, where the gate structure includes (i) a gate electrode and (ii) a gate dielectric between the body and the gate electrode. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：US11469299B2

公开(公告)日：2022-10-11

申请号：US16146785

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax Crum ,  Patrick Keys ,  Tahir Ghani ,  Susmita Ghose ,  Ted Cook, Jr.

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11411110B2

公开(公告)日：2022-08-09

申请号：US17499605

申请日：2021-10-12

Applicant: Intel Corporation

Inventor： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32 ,  H01L29/165

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US20220238714A1

公开(公告)日：2022-07-28

申请号：US17723582

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US10396201B2

公开(公告)日：2019-08-27

申请号：US14912594

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.