利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.015 秒)

    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT
    1.
    发明公开
    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT 审中-公开

    公开(公告)号：US20230420578A1

    公开(公告)日：2023-12-28

    申请号：US17848660

    申请日：2022-06-24

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

    IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

    摘要： A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

    CONDUCTIVE CONTACTS WRAPPED AROUND EPITAXIAL SOURCE OR DRAIN REGIONS
    3.
    发明公开
    CONDUCTIVE CONTACTS WRAPPED AROUND EPITAXIAL SOURCE OR DRAIN REGIONS 审中-公开

    公开(公告)号：US20230275124A1

    公开(公告)日：2023-08-31

    申请号：US17681263

    申请日：2022-02-25

    申请人： Intel Corporation

    发明人： Leonard P. Guler ,  Gilbert Dewey ,  Saurabh Morarka ,  Sikandar Abbas ,  Mohammad Hasan

    IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

    CPC分类号： H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/088

    摘要： Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.

    Gate-all-around integrated circuit structures including varactors
    4.
    发明授权
    Gate-all-around integrated circuit structures including varactors 有权

    公开(公告)号：US11417781B2

    公开(公告)日：2022-08-16

    申请号：US16830112

    申请日：2020-03-25

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

    IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

    摘要： Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

    FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS
    7.
    发明申请
    FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS 审中-公开

    公开(公告)号：US20200259018A1

    公开(公告)日：2020-08-13

    申请号：US16270826

    申请日：2019-02-08

    申请人： Intel Corporation

    发明人： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

    IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40

    摘要： Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

    PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT
    10.
    发明公开
    PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230299135A1

    公开(公告)日：2023-09-21

    申请号：US17697129

    申请日：2022-03-17

    申请人： Intel Corporation

    发明人： Leonard P. Guler ,  Tahir Ghani ,  Saurabh Morarka ,  Charles H. Wallace

    IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088

    CPC分类号： H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656 ,  H01L27/0886

    摘要： Techniques are provided herein to form an integrated circuit having any number of partial gate cut structures between adjacent semiconductor devices. Neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a partial gate cut structure is present between a given pair of neighboring semiconductor devices. The partial gate cut structure acts as a dielectric pillar between the semiconductor structures that allows the conductive gate layer (from the gate structure) to extend above and/or below it such that the gates of each of the semiconductor devices remain electrically coupled together. The gate cut structure itself removes a portion of the gate layer from between the semiconductor devices, thus reducing parasitic capacitance.