公开(公告)号：US20230062922A1

公开(公告)日：2023-03-02

申请号：US17458097

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L29/778 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66

Abstract: Gallium nitride (GaN) selective epitaxial windows for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

公开(公告)号：US20230050491A1

公开(公告)日：2023-02-16

申请号：US17403041

申请日：2021-08-16

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/06

Abstract: High voltage metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：US20220102344A1

公开(公告)日：2022-03-31

申请号：US17033509

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/092 ,  H01L29/40 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06 ,  H01L23/538

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220102339A1

公开(公告)日：2022-03-31

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220093790A1

公开(公告)日：2022-03-24

申请号：US17030221

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Robert EHLERT ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Sandrine CHARUE-BAKKER

IPC: H01L29/78 ,  H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/40

Abstract: Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

公开(公告)号：US20210202374A1

公开(公告)日：2021-07-01

申请号：US17202281

申请日：2021-03-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L23/532

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

公开(公告)号：US20200066848A1

公开(公告)日：2020-02-27

申请号：US16074377

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20190393311A1

公开(公告)日：2019-12-26

申请号：US16016406

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

公开(公告)号：US20190260342A1

公开(公告)日：2019-08-22

申请号：US16346099

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Paul B. FISCHER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H03H3/04 ,  H03H9/17

Abstract: Embodiments of the invention include microelectronic devices, resonators, and methods of fabricating the microelectronic devices. In one embodiment, a microelectronic device includes a substrate and a plurality of cavities integrated with the substrate. A plurality of vertically oriented resonators are formed with each resonator being positioned in a cavity. Each resonator includes a crystalline or single crystal piezoelectric film.

公开(公告)号：US20180358406A1

公开(公告)日：2018-12-13

申请号：US15778603

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Bruce A. BLOCK ,  Paul B. FISCHER ,  Nebil TANZI ,  Gregory CHANCE ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L27/20 ,  H03H9/17 ,  H03H3/02 ,  H03H9/56 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.