公开(公告)号：US20240203979A1

公开(公告)日：2024-06-20

申请号：US18085122

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based transistor structure is above substrate, the silicon-based transistor structure at a level above the gate of the GaN device in a region outside of the GaN device.

公开(公告)号：US20230047449A1

公开(公告)日：2023-02-16

申请号：US17402054

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Nicole K. THOMAS ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Pratik KOIRALA ,  Nityan NAIR

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02

Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

公开(公告)号：US20240213140A1

公开(公告)日：2024-06-27

申请号：US18088541

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ibrahim BAN ,  Nityan NAIR ,  Thomas HOFF

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226

Abstract: Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

公开(公告)号：US20240203815A1

公开(公告)日：2024-06-20

申请号：US18085106

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Han Wui THEN

IPC: H01L23/34 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/34 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based diode structure or a silicon-based thin-film resistor is above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the GaN device in a region between the gate and the drain of the GaN device.

公开(公告)号：US20230069054A1

公开(公告)日：2023-03-02

申请号：US17410257

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Souvik GHOSH ,  Han Wui THEN ,  Pratik KOIRALA ,  Tushar TALUKDAR ,  Paul NORDEEN ,  Nityan NAIR ,  Marko RADOSAVLJEVIC ,  Ibrahim BAN ,  Kimin JUN ,  Jay GUPTA ,  Paul B. FISCHER ,  Nicole K. THOMAS ,  Thomas HOFF ,  Samuel James BADER

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

公开(公告)号：US20230062922A1

公开(公告)日：2023-03-02

申请号：US17458097

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L29/778 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66

Abstract: Gallium nitride (GaN) selective epitaxial windows for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

公开(公告)号：US20240213118A1

公开(公告)日：2024-06-27

申请号：US18088545

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Heli Chetanbhai VORA ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Thomas HOFF ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Paul NORDEEN ,  Nityan NAIR

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01P3/00

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01P3/003 ,  H01L2223/6627

Abstract: Gallium nitride (GaN) devices with through-silicon vias for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, the layer including gallium and nitrogen above a silicon substrate. A backside structure is below the silicon substrate and opposite the layer including gallium and nitrogen, the backside structure including conductive features and dielectric structures. The integrated circuit structure also includes a plurality of through-silicon via power bars having a staggered arrangement, individual ones of the through-silicon via power bars extending through the layer including gallium and nitrogen and through the silicon substrate to a corresponding one of the conductive features of the backside structure, and individual ones of the through-silicon via power bars having a tapered portion coupled to an essentially vertical portion.

公开(公告)号：US20240203978A1

公开(公告)日：2024-06-20

申请号：US18085116

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Harish KRISHNAMURTHY ,  Han Wui THEN ,  William J. LAMBERT ,  Jingshu YU

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based clamp structure is above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.

公开(公告)号：US20230097805A1

公开(公告)日：2023-03-30

申请号：US17485232

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a channel, where the channel comprises a first semiconductor material. In an embodiment, a source contact is at a first end of the channel, and a drain contact at a second end of the channel. In an embodiment, a gate electrode is between the source contact and the drain contact, and a field plate extends from the gate electrode towards the drain contact. In an embodiment, a plurality of protrusions extend out from the field plate towards the channel, where the protrusions comprise a second semiconductor material

公开(公告)号：US20240222440A1

公开(公告)日：2024-07-04

申请号：US18089919

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN ,  Ibrahim BAN ,  Heli Chetanbhai VORA ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L21/02 ,  H01L21/18 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/0254 ,  H01L21/185 ,  H01L21/32051 ,  H01L29/0607 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a GaN layer, where the silicon layer includes a first portion of a device, for example a transistor, and the GaN layer includes a second portion of the device. Other embodiments may be described and/or claimed.