公开(公告)号：US20190042455A1

公开(公告)日：2019-02-07

申请号：US16136036

申请日：2018-09-19

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F12/0891 ,  G06F12/0868 ,  G06F12/0815 ,  G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can include ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled lanes configured in a first direction and a second set of bundled lanes configured in a second direction, the second direction is opposite to the first direction, the first set of bundled lanes comprises an equal number of lanes as the second set of bundled lanes. An input/output (I/O) bridge logic implemented at least partially in hardware can receive across the multilane link an cache invalidation request received on a port compliant with an I/O protocol. A memory controller logic implemented at least partially in hardware can invalidate a cache line based on receiving the cache invalidation request on the I/O protocol. The memory controller can transmit across the multilane link a memory invalidation response message on a port compliant with a device-attached memory access protocol.

公开(公告)号：US20170255553A1

公开(公告)日：2017-09-07

申请号：US15602603

申请日：2017-05-23

Applicant: INTEL CORPORATION

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.

公开(公告)号：US09727475B2

公开(公告)日：2017-08-08

申请号：US14497740

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Yen-Cheng Liu ,  Joseph Nuzman ,  Ashok Jagannathan ,  Bahaa Fahim ,  Nithiyanandan Bashyam

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F2212/452

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

公开(公告)号：US11347662B2

公开(公告)日：2022-05-31

申请号：US15721777

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US11016894B2

公开(公告)日：2021-05-25

申请号：US15670171

申请日：2017-08-07

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Ishwar Agarwal ,  Stephen Van Doren

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0817

Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

公开(公告)号：US20200334179A1

公开(公告)日：2020-10-22

申请号：US16840266

申请日：2020-04-03

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Peeyush Purohit ,  Nitish Paliwal ,  Archana Srinivasan

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

公开(公告)号：US20200021540A1

公开(公告)日：2020-01-16

申请号：US16582224

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Rajesh Sankaran ,  Ishwar Agarwal ,  Nitish Paliwal

IPC: H04L12/935 ,  H04L29/06

Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.

公开(公告)号：US10437616B2

公开(公告)日：2019-10-08

申请号：US15396529

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh Sankaran ,  Stephen Van Doren

IPC: G06F9/455 ,  G06F9/50

Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.

公开(公告)号：US20190095363A1

公开(公告)日：2019-03-28

申请号：US16141729

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Peeyush Purohit ,  Nitish Paliwal ,  Archana Srinivasan

IPC: G06F13/16 ,  G06F13/42 ,  G06F11/10

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

公开(公告)号：US09940238B2

公开(公告)日：2018-04-10

申请号：US15602603

申请日：2017-05-23

Applicant: INTEL CORPORATION

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC: G06F12/08 ,  G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.