公开(公告)号：US20220393960A1

公开(公告)日：2022-12-08

申请号：US17846947

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Peter McCarthy ,  Chris MacNamara ,  John Browne ,  Liang J. Ma ,  Liam Day

IPC: H04L43/10 ,  H04L41/0833 ,  H04L43/022 ,  H04L43/16 ,  G06F1/3209

Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

公开(公告)号：US20220368348A1

公开(公告)日：2022-11-17

申请号：US17870659

申请日：2022-07-21

Applicant: INTEL CORPORATION

Inventor： Laurent Coquerel ,  Fei Wang ,  John Browne ,  Smita Kumar ,  Declan Doherty ,  Marlow Weston ,  Reshma Pattan

IPC: H03M7/30

Abstract: An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.

公开(公告)号：US20160306416A1

公开(公告)日：2016-10-20

申请号：US14688019

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： John Browne ,  Chris Macnamara

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3209 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/4893 ,  G06F2209/548 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In an embodiment, a system includes a processor that includes a plurality of cores and a plurality of queue. Each queue includes storage locations to store packets to be processed by at least one of the cores. Each queue has a corresponding state that is one of active and inactive. Each active queue is enabled to store an incoming packet, and each inactive queue is disabled from storage of the incoming packet. Each queue has a corresponding queue depth that includes a count of occupied storage locations of the queue. The system also includes packet distribution logic to determine whether to change the state of a first queue of the plurality of queues from a first state to a second state based on a total queue depth that includes a sum of the queue depths of the active queues. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括包括多个核心和多个队列的处理器。 每个队列包括用于存储要被至少一个核心处理的分组的存储位置。 每个队列都有一个对应的状态，它是一个活动和非活动状态。 启用每个活动队列以存储传入的数据包，并且禁止每个不活动队列存储进入的数据包。 每个队列具有对应的队列深度，其包括队列占用的存储位置的计数。 该系统还包括分组分配逻辑，用于基于包括活动队列的队列深度的总和的总队列深度来确定是否将多个队列中的第一队列的状态从第一状态改变到第二状态。 描述和要求保护其他实施例。