公开(公告)号：US10372450B2

公开(公告)日：2019-08-06

申请号：US15647123

申请日：2017-07-11

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Daehyun Kim ,  Tin-Fook Ngai ,  Jayashankar Bharadwaj ,  Albert Hartono ,  Sara Baghsorkhi ,  Nalini Vasudevan

IPC: G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

公开(公告)号：US20170205863A1

公开(公告)日：2017-07-20

申请号：US14995263

申请日：2016-01-14

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Yuxin Bai

IPC: G06F1/28 ,  G06N99/00

CPC classification number: G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06N99/005 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information, and a second logic to receive the performance monitoring information and dynamically update the power management model according to a reinforcement learning process. Other embodiments are described and claimed.

公开(公告)号：US20160139897A1

公开(公告)日：2016-05-19

申请号：US15005781

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J. Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括在执行具有迭代的原始循环之前，经由处理器分析原始循环的迭代，识别原始循环的第一迭代和原始循环的第二迭代之间的依赖关系 循环，在识别依赖性之后，基于所识别的依赖关系对原始循环的第一组迭代进行矢量化以形成矢量化循环，以及基于所识别的依赖关系来设置矢量化循环的动态调整值。

公开(公告)号：US20150228091A1

公开(公告)日：2015-08-13

申请号：US14693056

申请日：2015-04-22

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G06T11/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20140237303A1

公开(公告)日：2014-08-21

申请号：US13997664

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Jayashankar Bharadwaj ,  Victor W. Lee ,  Kim Daehyun ,  Nalini Vasudevan ,  Tin-Fook Ngai ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

Abstract translation: 描述了用于检测和响应处理器中的故障状况的装置和方法。 例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且跟随检测到的故障状况，设置输出屏蔽寄存器中的位以指示检测到的故障状况。