公开(公告)号：US09232645B2

公开(公告)日：2016-01-05

申请号：US14087341

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Jinwoo Choi ,  Daniel M. Dreps ,  Rohan U. Mandrekar

IPC: H01L23/528 ,  H05K1/02 ,  C04B37/00 ,  H05K1/03 ,  H05K3/46 ,  H01L21/48 ,  H05K3/12 ,  H01L23/522 ,  H05K1/09 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24

CPC classification number: H05K1/0298 ,  B32B18/00 ,  C04B37/006 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/68 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/005 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/1291 ,  H05K3/245 ,  H05K3/4667 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/09272 ,  H05K2201/09709 ,  H05K2203/0126 ,  H05K2203/063 ,  Y10T156/10 ,  H01L2924/00

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，更具体地涉及用于在多层玻璃 - 陶瓷（MLC）模块中制造差分布线图案的结构和方法。 公开了一种形成具有彼此直接形成的交错或偏移成对的层的MLC的结构和方法。 另外，公开了一种形成具有周期性反转极性的具有交错或偏移的线对的层的MLC的结构和方法。

公开(公告)号：US20150271926A1

公开(公告)日：2015-09-24

申请号：US14731815

申请日：2015-06-05

Applicant: International Business Machines Corporation

Inventor： John L. Colbert ,  Daniel M. Dreps ,  Paul M. Harvey ,  Rohan U. Mandrekar

IPC: H05K3/32 ,  H05K7/10

CPC classification number: H05K3/325 ,  G06F1/183 ,  G06F1/20 ,  H01L23/36 ,  H01L23/49827 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/15313 ,  H05K7/1061 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

公开(公告)号：US20150144382A1

公开(公告)日：2015-05-28

申请号：US14087341

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Jinwoo Choi ,  Daniel M. Dreps ,  Rohan U. Mandrekar

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K3/12 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0298 ,  B32B18/00 ,  C04B37/006 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/68 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/005 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/1291 ,  H05K3/245 ,  H05K3/4667 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/09272 ,  H05K2201/09709 ,  H05K2203/0126 ,  H05K2203/063 ,  Y10T156/10 ,  H01L2924/00

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，更具体地涉及用于在多层玻璃 - 陶瓷（MLC）模块中制造差分布线图案的结构和方法。 公开了一种形成具有彼此直接形成的交错或偏移成对的层的MLC的结构和方法。 另外，公开了一种形成具有周期性反转极性的具有交错或偏移的线对的层的MLC的结构和方法。