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    Method and apparatus for high bandwidth dictionary compression technique using set update dictionary update policy
    28.
    发明授权
    Method and apparatus for high bandwidth dictionary compression technique using set update dictionary update policy 有权
    使用集更新字典更新策略的高带宽字典压缩技术的方法和装置

    公开(公告)号：US09514085B2

    公开(公告)日：2016-12-06

    申请号：US13638132

    申请日：2011-10-01

    Applicant: Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    Inventor： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    IPC: G06F13/42 ,  H03M7/00 ,  H03M7/30 ,  G06F13/00

    CPC classification number: G06F13/42 ,  G06F13/00 ,  H03M7/00 ,  H03M7/3088

    Abstract: Method, apparatus, and systems employing novel dictionary entry replacement schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

    Abstract translation: 用于基于字典的高带宽无损压缩的新字典条目替换方案的方法，装置和系统。 具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。 压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。 字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。 公开了用于条目替换的各种方案以及延迟字典更新技术。 该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。

    INSTRUCTIONS AND LOGIC TO PROVIDE ATOMIC RANGE OPERATIONS
    29.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE ATOMIC RANGE OPERATIONS 审中-公开
    说明和逻辑提供原子范围操作

    公开(公告)号：US20160283237A1

    公开(公告)日：2016-09-29

    申请号：US14671914

    申请日：2015-03-27

    Applicant: Ilan Pardo ,  Oren Ben-Kiki ,  Arch D. Robison ,  Nadav Chachmon ,  James H. Cownie

    Inventor： Ilan Pardo ,  Oren Ben-Kiki ,  Arch D. Robison ,  Nadav Chachmon ,  James H. Cownie

    IPC: G06F9/30 ,  G06F9/355

    CPC classification number: G06F9/3001 ,  G06F9/30018 ,  G06F9/3004 ,  G06F9/526

    Abstract: Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.

    Abstract translation: 说明和逻辑在多处理系统中提供原子范围操作。 在一个实施例中，原子范围修改指令指定一组范围索引的地址。 该指令锁定对范围索引的访问，并加载范围索引以检查范围大小。 将范围大小与足以执行范围修改的大小进行比较。 如果范围大小足以进行范围修改，则执行范围修改，并且将范围索引集合中的一个或多个修改的范围索引存储回存储器。 否则当范围大小不足以执行所述范围修改时，设置错误信号。 响应于原子范围修改指令的完成，对范围索引集的访问被解锁。 实施例可以包括原子增量下一个指令，添加下一个指令，递减结束指令和/或减去结束指令。

    APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCELERATORS
    30.
    发明申请
    APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCELERATORS 审中-公开
    用于可切换同步硬件加速器的设备和方法

    公开(公告)号：US20140189333A1

    公开(公告)日：2014-07-03

    申请号：US13730143

    申请日：2012-12-28

    Applicant: Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

    Inventor： Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

    IPC: G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/30189 ,  G06F9/3881

    Abstract: A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.

    Abstract translation: 一种处理器，包括执行逻辑，以执行包括调用加速器命令的加速器调用指令的第一线程; 加速器，其响应于加速器命令执行加速器线程，加速器，用于将与加速器线程相关联的状态数据存储在存储器中的应用存储器区域中，其中在执行加速器线程之前，加速器将锁定条目转换为 与加速器线程相关联的后备缓冲器（TLB），以防止否则可能导致的异常。

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