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1.发明申请METHOD, SYSTEM, AND APPARATUS FOR REROUTING INTERRUPTS IN A MULTI-CORE PROCESSOR 有权用于在多核处理器中进行中断的方法，系统和设备公开(公告)号：US20090172423A1
公开(公告)日：2009-07-02
申请号：US11967799
申请日：2007-12-31
申请人： Justin Song , Devadatta V. Bodas , Ohad Falik , Alon Naveh , Ilan Pardo , Anil Aggarwal , Sridhar Muthrasanallur , James B. Crossland
发明人： Justin Song , Devadatta V. Bodas , Ohad Falik , Alon Naveh , Ilan Pardo , Anil Aggarwal , Sridhar Muthrasanallur , James B. Crossland
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F9/4812 , G06F9/5044 , G06F9/5094 , Y02D10/152 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以将中断路由到多核系统的多个核心的第一核心。 如果第一核心处于空闲或低功率状态，或处于等于或低于阈值功率状态的功率状态，则可以找到处于最小空闲状态的核心。 中断可以在最不空闲状态下由核心重新路由到并处理。 可以基于例如功率状态或其他特性对多核系统中的核进行额定，并且可以基于这些额定值分配中断。 描述和要求保护其他实施例。
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2.发明授权Method, system, and apparatus for rerouting interrupts in a multi-core processor 有权用于在多核处理器中重新路由中断的方法，系统和装置公开(公告)号：US07962771B2
公开(公告)日：2011-06-14
申请号：US11967799
申请日：2007-12-31
申请人： Justin Song , Devadatta V. Bodas , Ohad Falik , Alon Naveh , Ilan Pardo , Anil Aggarwal , Sridhar Muthrasanallur , James B. Crossland
发明人： Justin Song , Devadatta V. Bodas , Ohad Falik , Alon Naveh , Ilan Pardo , Anil Aggarwal , Sridhar Muthrasanallur , James B. Crossland
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F9/4812 , G06F9/5044 , G06F9/5094 , Y02D10/152 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以将中断路由到多核系统的多个核心的第一核心。 如果第一核心处于空闲或低功率状态，或处于等于或低于阈值功率状态的功率状态，则可以找到处于最小空闲状态的核心。 中断可以在最不空闲状态下由核心重新路由到并处理。 可以基于例如功率状态或其他特性对多核系统中的核进行额定，并且可以基于这些额定值分配中断。 描述和要求保护其他实施例。
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公开(公告)号：US20140304488A1
公开(公告)日：2014-10-09
申请号：US14312669
申请日：2014-06-23
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
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公开(公告)号：US20080301398A1
公开(公告)日：2008-12-04
申请号：US11757103
申请日：2007-06-01
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
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公开(公告)号：US08799620B2
公开(公告)日：2014-08-05
申请号：US11757103
申请日：2007-06-01
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
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6.发明授权公开(公告)号：US07627706B2
公开(公告)日：2009-12-01
申请号：US11850782
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。
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公开(公告)号：US20090070511A1
公开(公告)日：2009-03-12
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
IPC分类号： G06F13/24
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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公开(公告)号：US07769938B2
公开(公告)日：2010-08-03
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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9.发明授权Mechanism for processor power state aware distribution of lowest priority interrupts 失效处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07761720B2
公开(公告)日：2010-07-20
申请号：US11704760
申请日：2007-02-09
IPC分类号： G06F1/26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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10.发明授权Mechanism for processor power state aware distribution of lowest priority interrupt 有权处理器电源状态识别分配最低优先级中断的机制公开(公告)号：US07191349B2
公开(公告)日：2007-03-13
申请号：US10330622
申请日：2002-12-26
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。
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