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    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION
    21.
    发明申请
    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION 审中-公开

    公开(公告)号：US20200349313A1

    公开(公告)日：2020-11-05

    申请号：US16930424

    申请日：2020-07-16

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

    Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

    Hardware monitor to verify memory units
    23.
    发明授权
    Hardware monitor to verify memory units 有权

    公开(公告)号：US10580511B2

    公开(公告)日：2020-03-03

    申请号：US15340726

    申请日：2016-11-01

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G11C29/00 ,  G11C29/38 ,  G06F11/22 ,  G06F11/30 ,  G06F11/34 ,  G11C29/12 ,  G11C29/44 ,  G11C29/04

    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

    Livelock Detection in a Hardware Design Using Formal Evaluation Logic
    24.
    发明申请
    Livelock Detection in a Hardware Design Using Formal Evaluation Logic 审中-公开

    公开(公告)号：US20190272350A1

    公开(公告)日：2019-09-05

    申请号：US16419734

    申请日：2019-05-22

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F17/50 ,  G06F11/30 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

    Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

    Assessing Performance of a Hardware Design Using Formal Evaluation Logic
    25.
    发明申请
    Assessing Performance of a Hardware Design Using Formal Evaluation Logic 审中-公开

    公开(公告)号：US20190272349A1

    公开(公告)日：2019-09-05

    申请号：US16414594

    申请日：2019-05-16

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F17/50 ,  G06F11/34 ,  G06F11/30 ,  G06F11/36

    Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

    Assessing performance of a hardware design using formal evaluation logic
    26.
    发明授权
    Assessing performance of a hardware design using formal evaluation logic 有权

    公开(公告)号：US10331831B2

    公开(公告)日：2019-06-25

    申请号：US15340450

    申请日：2016-11-01

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F17/50 ,  G06F11/36 ,  G06F11/30 ,  G06F11/34

    Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

    Arbiter Verification
    28.
    发明申请
    Arbiter Verification 有权
    仲裁者验证

    公开(公告)号：US20160210381A1

    公开(公告)日：2016-07-21

    申请号：US14920445

    申请日：2015-10-22

    Applicant: Imagination Technologies Limited

    Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

    IPC: G06F17/50

    CPC classification number: G06F13/364 ,  G06F13/1621 ,  G06F13/3625 ,  G06F13/4252 ,  G06F13/4256 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045

    Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

    Abstract translation: 验证硬件设计中仲裁器的操作。 仲裁器在多个时钟周期内接收多个请求，包括被监视的请求，并以优先顺序输出请求。 识别在每个时钟周期中由仲裁器接收和输出的请求。 然后，使用基于在每个时钟周期中输入到仲裁器并从仲裁器输出的请求而更新的计数器跟踪观察请求相对于仲裁器中的其他未决请求的优先级，以及识别由所述仲裁器接收的请求的相对优先级的掩码 仲裁者在同一个时钟周期。 使用断言来确认仲裁器的操作，该断言建立从仲裁器输出监视请求的计数器与时钟周期之间的关系。

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