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公开(公告)号：US20190339360A1
公开(公告)日：2019-11-07
申请号：US16402268
申请日：2019-05-03
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , David Addison , Markus Bichl , Dian Tresna Nugraha , Andre Roger
IPC: G01S7/35
Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
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公开(公告)号：US12189052B2
公开(公告)日：2025-01-07
申请号：US17324487
申请日：2021-05-19
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Simon Achatz , Dian Tresna Nugraha , Ljudmil Anastasov , Markus Bichl , Mayeul Jeannin , Farhan Bin Khalid
IPC: G01S7/35 , G01S7/288 , G01S13/44 , G01S13/536 , G01S13/58 , G01S13/931
Abstract: It is suggested to process radar signals including (i) determining a variation of at least one radar parameter provided from at least one radar device; (ii) determining an estimated value of at least one radar parameter from an error compensation vector; and (iii) determining a safety condition based on the variation and the estimated value for the respective radar parameter.
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公开(公告)号：US12155434B2
公开(公告)日：2024-11-26
申请号：US17481517
申请日：2021-09-22
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Farhan Bin Khalid , Dian Tresna Nugraha , Romain Ygnace
Abstract: A method for a radar system having a plurality of antennas is provided. The method includes processing a plurality of radar signals for determining a distance between the radar system and at least one target and a velocity of the at least one target, thereby forming a plurality of processed radar signals. Each radar signal of the plurality of radar signals is received by an associated antenna of the plurality of antennas. The plurality of processed radar signals are digitally beamformed for at least one beam direction, thereby forming a plurality of beamformed radar signals. The plurality of beamformed radar signals are summed from the plurality of antennas per beam direction.
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公开(公告)号：US20240310481A1
公开(公告)日：2024-09-19
申请号：US18183263
申请日：2023-03-14
Applicant: Infineon Technologies AG
Inventor： David Addison , Dyson Wilkes , Markus Bichl , Sandeep Vangipuram
CPC classification number: G01S7/356 , G01S13/584
Abstract: A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.
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公开(公告)号：US20230138972A1
公开(公告)日：2023-05-04
申请号：US17512984
申请日：2021-10-28
Applicant: Infineon Technologies AG
Inventor： Ajayan Vijayakumaran Nair , David Michael Addison , Markus Bichl , Moustafa Samy Abdelkhalek Ahmed Emara , Andre Roger , Dyson Wilkes
IPC: G01S7/35
Abstract: In some methods, sampled values based on a reception signal are stored in rows and columns of a memory array. A first 1-dimensional (1D) detector is moved in a first direction over the memory array. The first 1D detector includes a first cell under test and first and second training cells on opposite sides of the first cell under test. The first cell under test and the first and second training cells of the first 1D detector being aligned in the first direction. A second 1D detector is moved over the memory array. The second 1D detector includes a second cell under test and third and fourth training cells on opposite sides of the second cell under test. The second cell under test and the third and fourth training cells of the second 1D detector are aligned in a second direction that is perpendicular to the first direction.
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Patent Agency Ranking
公开(公告)号：US11639983B2
公开(公告)日：2023-05-02
申请号：US17302328
申请日：2021-04-30
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Dian Tresna Nugraha , Romain Ygnace
Abstract: A radar sensor is described herein. In accordance with one example embodiment the radar sensor includes a transmitter for transmitting an RF signal and a receiver configured to receive a respective back-scattered signal from at least one radar target and to provide a corresponding digital radar signal. The radar sensor further includes a processor configured to convert the digital radar signal into the frequency do-main thus providing respective frequency domain data and to compress the frequency domain data. A communication interface is configured to transmit the compressed frequency domain data via a communication link operably coupled to the communication interface. Furthermore, respective and related radar methods and systems are described.
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公开(公告)号：US11525885B2
公开(公告)日：2022-12-13
申请号：US16402268
申请日：2019-05-03
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , David Addison , Markus Bichl , Dian Tresna Nugraha , Andre Roger
IPC: G01S7/35
Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
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公开(公告)号：US20210364622A1
公开(公告)日：2021-11-25
申请号：US17324487
申请日：2021-05-19
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Simon Achatz , Dian Tresna Nugraha , Ljudmil Anastasov , Markus Bichl , Mayeul Jeannin , Farhan Bin Khalid
IPC: G01S13/44 , G01S7/288 , G01S13/931
Abstract: It is suggested to process radar signals including (i) determining a variation of at least one radar parameter provided from at least one radar device; (ii) determining an estimated value of at least one radar parameter from an error compensation vector; and (iii) determining a safety condition based on the variation and the estimated value for the respective radar parameter.
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公开(公告)号：US11121810B2
公开(公告)日：2021-09-14
申请号：US16585811
申请日：2019-09-27
Applicant: Infineon Technologies AG
Inventor： Ljudmil Anastasov , Markus Bichl
IPC: H04L1/00 , H04B7/0413 , H04L7/033 , H04L25/49 , G01S7/00
Abstract: A synchronous communication interface includes at least one data channel configured to carry a data signal comprising a plurality of data units; a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information. The circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.
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公开(公告)号：US10996311B2
公开(公告)日：2021-05-04
申请号：US16049982
申请日：2018-07-31
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Dian Tresna Nugraha , Romain Ygnace
Abstract: A radar sensor is described herein. In accordance with one example embodiment the radar sensor includes a transmitter for transmitting an RF signal and a receiver configured to receive a respective back-scattered signal from at least one radar target and to provide a corresponding digital radar signal. The radar sensor further includes a processor configured to convert the digital radar signal into the frequency do-main thus providing respective frequency domain data and to compress the frequency domain data. A communication interface is configured to transmit the compressed frequency domain data via a communication link operably coupled to the communication interface. Furthermore, respective and related radar methods and systems are described.
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