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    Systems, devices, and methods for dynamic allocation
    1.
    发明授权
    Systems, devices, and methods for dynamic allocation 有权

    公开(公告)号：US12287862B2

    公开(公告)日：2025-04-29

    申请号：US17981583

    申请日：2022-11-07

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

    IPC: G06F21/44 ,  G06F21/60 ,  G06F21/62 ,  G06F21/71 ,  G06F21/78

    Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

    HARDWARE BOUNDARY CHECKING FOR RADAR
    2.
    发明公开
    HARDWARE BOUNDARY CHECKING FOR RADAR 审中-公开

    公开(公告)号：US20240310480A1

    公开(公告)日：2024-09-19

    申请号：US18183292

    申请日：2023-03-14

    Applicant: Infineon Technologies AG

    Inventor： David Addison ,  Dyson Wilkes ,  Markus Bichl ,  Sandeep Vangipuram

    IPC: G01S7/35 ,  G01S13/58

    CPC classification number: G01S7/354 ,  G01S7/356 ,  G01S13/584

    Abstract: A radar system including a direct memory access (DMA). The DMA includes a bus interface including control/status registers and data-in/data-out registers. The DMA also includes potential object queue memory coupled to the bus interface, and a potential object queue logic coupled to the potential object queue memory. The DMA also includes boundary checking circuitry configured to detect whether any portion of a DMA read configuration is greater than a maximum range bin or less than a minimum range bin. The boundary checking circuitry detects whether any portion of the DMA read configuration is greater than a maximum Doppler bin or less than a minimum Doppler bin.

    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION
    3.
    发明公开
    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION 审中-公开

    公开(公告)号：US20230161862A1

    公开(公告)日：2023-05-25

    申请号：US17981583

    申请日：2022-11-07

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

    IPC: G06F21/44

    CPC classification number: G06F21/44

    Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

    HARDWARE GENERATION OF 3D DMA CONFIGURATIONS
    4.
    发明公开
    HARDWARE GENERATION OF 3D DMA CONFIGURATIONS 审中-公开

    公开(公告)号：US20240310481A1

    公开(公告)日：2024-09-19

    申请号：US18183263

    申请日：2023-03-14

    Applicant: Infineon Technologies AG

    Inventor： David Addison ,  Dyson Wilkes ,  Markus Bichl ,  Sandeep Vangipuram

    IPC: G01S7/35 ,  G01S13/58

    CPC classification number: G01S7/356 ,  G01S13/584

    Abstract: A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.

    Flexible support for device emulation and bank swapping
    6.
    发明授权
    Flexible support for device emulation and bank swapping 有权

    公开(公告)号：US12032960B2

    公开(公告)日：2024-07-09

    申请号：US17708882

    申请日：2022-03-30

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Ashley Farrall

    IPC: G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/30018 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/30145 ,  G06F12/0238 ,  G06F2212/7201

    Abstract: A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.

    PROCESSING OF INTERRUPTS
    7.
    发明公开
    PROCESSING OF INTERRUPTS 审中-公开

    公开(公告)号：US20230342187A1

    公开(公告)日：2023-10-26

    申请号：US18302053

    申请日：2023-04-18

    Applicant: Infineon Technologies AG

    Inventor： Frank Hellwig ,  Sandeep Vangipuram

    IPC: G06F9/48 ,  G06F13/28

    CPC classification number: G06F9/4818 ,  G06F13/28

    Abstract: It is suggested to process an interrupt event as follows: (i) receiving an interrupt event at a service request node; (ii) providing, by the service request node, an interrupt service request based on the interrupt event, and a security information; and (iii) forwarding the interrupt service request to an interrupt service provider.

    FLEXIBLE SUPPORT FOR DEVICE EMULATION AND BANK SWAPPING
    8.
    发明公开
    FLEXIBLE SUPPORT FOR DEVICE EMULATION AND BANK SWAPPING 审中-公开

    公开(公告)号：US20230315448A1

    公开(公告)日：2023-10-05

    申请号：US17708882

    申请日：2022-03-30

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Ashley Farrall

    IPC: G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/30018 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/30145 ,  G06F12/0238 ,  G06F2212/7201

    Abstract: A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.

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